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74ACT573SC

P1-P3P4-P6P7-P9P10-P12P13-P13
74AC573, 74ACT573 — Octal Latch with 3-STATE Outputs
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC573, 74ACT573 Rev. 1.6.0
January 2008
74AC573, 74ACT573
Octal Latch with 3-STATE Outputs
Features
■
I
CC
and I
OZ
reduced by 50%
■
Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
■
Useful as input or output port for microprocessors
■
Functionally identical to 74AC373 and 74ACT373
■
3-STATE outputs for bus interfacing
■
Outputs source/sink 24mA
■
74ACT573 has TTL-compatible inputs
General Description
The 74AC573 and 74ACT573 are high-speed octal
latches with buffered common Latch Enable (LE) and
buffered common Output Enable (OE
) inputs.
The 74AC573 and 74ACT573 are functionally identical
to the 74AC373 and 74ACT373 but with inputs and
outputs on opposite sides.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Order Number
Package
Number Package Description
74AC573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"
Wide
74AC573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
74ACT573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"
Wide
74ACT573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
74ACT573PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC573, 74ACT573 Rev. 1.6.0 2
74AC573, 74ACT573 — Octal Latch with 3-STATE Outputs
Connection Diagram
Pin Description
Functional Description
The 74AC573 and 74ACT573 contain eight D-type
latches with 3-STATE output buffers. When the Latch
Enable (LE) input is HIGH, data on the D
n
inputs enters
the latches. In this condition the latches are transparent,
i.e., a latch output will change state each time its D-type
input changes. When LE is LOW the latches store the
information that was present on the D-type inputs a
setup time preceding the HIGH-to-LOW transition of LE.
The 3-STATE buffers are controlled by the Output
Enable (OE
) input. When OE is LOW, the buffers are
enabled. When OE
is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Logic Symbols
Truth Table
H
=
HIGH Voltage
L
=
LOW Voltage
Z
=
High Impedance
X
=
Immaterial
O
0
=
Previous O
0
before HIGH-to-LOW transition of
Latch Enable
Pin Names Description
D
0
–D
7
Data Inputs
LE Latch Enable Input
OE
3-STATE Output Enable Input
O
0
–O
7
3-STATE Latch Outputs
Inputs Outputs
OE LE D O
n
LHH H
LHL L
LLX O
0
HXX Z
IEEE/IEC
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC573, 74ACT573 Rev. 1.6.0 3
74AC573, 74ACT573 — Octal Latch with 3-STATE Outputs
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
P1-P3P4-P6P7-P9P10-P12P13-P13

74ACT573SC

Mfr. #:
Buy 74ACT573SC
Manufacturer:
ON Semiconductor
Description:
IC LATCH OCTAL 3 STATE 20-SOIC
Lifecycle:
New from this manufacturer.
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