NVT2001_NVT2002 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 27 January 2014 7 of 26
NXP Semiconductors
NVT2001; NVT2002
Bidirectional voltage level translator
7.2 Bidirectional translation
For the bidirectional clamping configuration (higher voltage to lower voltage or lower
voltage to higher voltage), the EN input must be connected to VREFB and both pins pulled
to HIGH side V
pu(D)
through a pull-up resistor (typically 200 k). This allows VREFB to
regulate the EN input. A filter capacitor on VREFB is recommended. The master output
driver can be totem pole or open-drain (pull-up resistors may be required) and the slave
device output can be totem pole or open-drain (pull-up resistors are required to pull the Bn
outputs to V
pu(D)
). However, if either output is totem-pole, data must be unidirectional or
the outputs must be 3-stateable and be controlled by some direction-control mechanism
to prevent HIGH-to-LOW contentions in either direction. If both outputs are open-drain, no
direction control is needed.
The reference supply voltage (V
ref(A)
) is connected to the processor core power supply
voltage. When VREFB is connected through a 200 k resistor to a 3.3 V to 5.5 V V
pu(D)
power supply, and V
ref(A)
is set between 1.0 V and (V
pu(D)
1 V), the output of each An
has a maximum output voltage equal to VREFA, and the output of each Bn has a
maximum output voltage equal to V
pu(D)
.
7.3 How to size pull-up resistor value
Sizing the pull-up resistor on an open-drain bus is specific to the individual application and
is dependent on the following driver characteristics:
The driver sink current
The V
OL
of driver
The V
IL
of the driver
Frequency of operation
The following tables can be used to estimate the pull-up resistor value in different use
cases so that the minimum resistance for the pull-up resistor can be found.
Table 6
, Table 7 and Table 8 contain suggested minimum values of pull-up resistors for
the PCA9306 and NVT20xx devices with typical voltage translation levels and drive
currents. The calculated values assume that both drive currents are the same.
V
OL
=V
IL
=0.1 V
CC
and accounts for a 5%V
CC
tolerance of the supplies, 1%
resistor values. It should be noted that the resistor chosen in the final application should
be equal to or larger than the values shown in Table 6
, Table 7 and Table 8 to ensure that
the pass voltage is less than 10 % of the V
CC
voltage, and the external driver should be
able to sink the total current from both pull-up resistors. When selecting the minimum
resistor value in Table 6
, Table 7 or Table 8, the drive current strength that should be
chosen should be the lowest drive current seen in the application and account for any
drive strength current scaling with output voltage. For the GTL devices, the resistance
table should be recalculated to account for the difference in ON resistance and bias
voltage limitations between V
CC(B)
and V
CC(A)
.
NVT2001_NVT2002 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 27 January 2014 8 of 26
NXP Semiconductors
NVT2001; NVT2002
Bidirectional voltage level translator
Table 6. Pull-up resistor minimum values, 3 mA driver sink current for PCA9306 and NVT20xx
A-side B-side
1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V
1.0 V R
pu(A)
= 750
R
pu(B)
= 750
R
pu(A)
=845
R
pu(B)
=845
R
pu(A)
= 976
R
pu(B)
= 976
R
pu(A)
= none
R
pu(B)
=887
R
pu(A)
= none
R
pu(B)
=1.18k
R
pu(A)
= none
R
pu(B)
=1.82k
1.2 V R
pu(A)
=931
R
pu(B)
=931
R
pu(A)
=1.02k
R
pu(B)
=1.02k
R
pu(A)
= none
R
pu(B)
=887
R
pu(A)
= none
R
pu(B)
=1.18k
R
pu(A)
= none
R
pu(B)
=1.82k
1.5 V R
pu(A)
=1.1k
R
pu(B)
=1.1k
R
pu(A)
= none
R
pu(B)
=866
R
pu(A)
= none
R
pu(B)
=1.18k
R
pu(A)
= none
R
pu(B)
=1.78k
1.8 V R
pu(A)
=1.47k
R
pu(B)
=1.47k
R
pu(A)
= none
R
pu(B)
=1.15k
R
pu(A)
= none
R
pu(B)
=1.78k
2.5 V R
pu(A)
=1.96k
R
pu(B)
=1.96k
R
pu(A)
= none
R
pu(B)
=1.78k
3.3 V R
pu(A)
= none
R
pu(B)
=1.74k
Table 7. Pull-up resistor minimum values, 10 mA driver sink current for PCA9306 and NVT20xx
A-side B-side
1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V
1.0 V R
pu(A)
= 221
R
pu(B)
= 221
R
pu(A)
=255
R
pu(B)
=255
R
pu(A)
= 287
R
pu(B)
= 287
R
pu(A)
= none
R
pu(B)
=267
R
pu(A)
= none
R
pu(B)
= 357
R
pu(A)
= none
R
pu(B)
=549
1.2 V R
pu(A)
=274
R
pu(B)
=274
R
pu(A)
= 309
R
pu(B)
= 309
R
pu(A)
= none
R
pu(B)
=267
R
pu(A)
= none
R
pu(B)
= 357
R
pu(A)
= none
R
pu(B)
=549
1.5 V R
pu(A)
= 332
R
pu(B)
= 332
R
pu(A)
= none
R
pu(B)
=261
R
pu(A)
= none
R
pu(B)
= 348
R
pu(A)
= none
R
pu(B)
=536
1.8 V R
pu(A)
=442
R
pu(B)
=442
R
pu(A)
= none
R
pu(B)
= 348
R
pu(A)
= none
R
pu(B)
=536
2.5 V R
pu(A)
= 590
R
pu(B)
= 590
R
pu(A)
= none
R
pu(B)
=523
3.3 V R
pu(A)
= none
R
pu(B)
=523
NVT2001_NVT2002 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 27 January 2014 9 of 26
NXP Semiconductors
NVT2001; NVT2002
Bidirectional voltage level translator
7.4 How to design for maximum frequency operation
The maximum frequency is limited by the minimum pulse width LOW and HIGH as well as
rise time and fall time. See Equation 1
as an example of the maximum frequency. The rise
and fall times are shown in Figure 8
.
(1)
The rise and fall times are dependent upon translation voltages, the drive strength, the
total node capacitance (C
L(tot)
) and the pull-up resistors (R
PU
) that are present on the bus.
The node capacitance is the addition of the PCB trace capacitance and the device
capacitance that exists on the bus. Because of the dependency of the external
components, PCB layout and the different device operating states the calculation of rise
and fall times is complex and has several inflection points along the curve.
The main component of the rise and fall times is the RC time constant of the bus line when
the device is in its two primary operating states: when device is in the ON state and it is
low-impedance, the other is when the device is OFF isolating the A-side from the B-side.
A description of the fall time applied to either An or Bn output going from HIGH to LOW is
as follows. Whichever side is asserted first, the B-side down must discharge to the V
CC(A)
voltage. The time is determined by the pull-up resistor, pull-down driver strength and the
Table 8. Pull-up resistor minimum values, 15 mA driver sink current for PCA9306 and NVT20xx
A-side B-side
1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V
1.0 V R
pu(A)
= 147
R
pu(B)
= 147
R
pu(A)
=169
R
pu(B)
=169
R
pu(A)
= 191
R
pu(B)
= 191
R
pu(A)
= none
R
pu(B)
=178
R
pu(A)
= none
R
pu(B)
= 237
R
pu(A)
= none
R
pu(B)
=365
1.2 V R
pu(A)
=182
R
pu(B)
=182
R
pu(A)
= 205
R
pu(B)
= 205
R
pu(A)
= none
R
pu(B)
=178
R
pu(A)
= none
R
pu(B)
= 237
R
pu(A)
= none
R
pu(B)
=365
1.5 V R
pu(A)
= 221
R
pu(B)
= 221
R
pu(A)
= none
R
pu(B)
=174
R
pu(A)
= none
R
pu(B)
= 232
R
pu(A)
= none
R
pu(B)
=357
1.8 V R
pu(A)
=294
R
pu(B)
=294
R
pu(A)
= none
R
pu(B)
= 232
R
pu(A)
= none
R
pu(B)
=357
2.5 V R
pu(A)
= 392
R
pu(B)
= 392
R
pu(A)
= none
R
pu(B)
=357
3.3 V R
pu(A)
= none
R
pu(B)
=348
Fig 8. An example waveform for maximum frequency
002aag912
t
r(actual)
t
f(actual)
GND
V
OL
V
IL
V
IH
V
CC
t
HIGH(min)
t
LOW(min)
1 / f
max
0.9 × V
CC
0.1 × V
CC

NVT2001GM,115

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Translation - Voltage Levels INTERFACE IC
Lifecycle:
New from this manufacturer.
Delivery:
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