1. General description
The NVT2001/02 are bidirectional voltage level translators operational from 1.0 V to 3.6 V
(V
ref(A)
) and 1.8 V to 5.5 V (V
ref(B)
), which allow bidirectional voltage translations between
1.0 V and 5 V without the need for a direction pin in open-drain or push-pull applications.
Bit widths ranging from 1-bit or 2-bit are offered for level translation application with
transmission speeds < 33 MHz for an open-drain system with a 50 pF capacitance and a
pull-up of 197 .
When the An or Bn port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the An and Bn ports. The low ON-state resistance (R
on
) of the
switch allows connections to be made with minimal propagation delay. Assuming the
higher voltage is on the Bn port when the Bn port is HIGH, the voltage on the An port is
limited to the voltage set by VREFA. When the An port is HIGH, the Bn port is pulled to the
drain pull-up supply voltage (V
pu(D)
) by the pull-up resistors. This functionality allows a
seamless translation between higher and lower voltages selected by the user without the
need for directional control.
When EN is HIGH, the translator switch is on, and the An I/O are connected to the Bn I/O,
respectively, allowing bidirectional data flow between ports. When EN is LOW, the
translator switch is off, and a high-impedance state exists between ports. The EN input
circuit is designed to be supplied by V
ref(B)
. To ensure the high-impedance state during
power-up or power-down, EN must be LOW.
All channels have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the switch is symmetrical.
The translator provides excellent ESD protection to lower voltage devices, and at the
same time protects less ESD-resistant devices.
2. Features and benefits
Provides bidirectional voltage translation with no direction pin
Less than 1.5 ns maximum propagation delay
Allows voltage level translation between:
1.0 V V
ref(A)
and 1.8 V, 2.5 V, 3.3 V or 5 V V
ref(B)
1.2 V V
ref(A)
and 1.8 V, 2.5 V, 3.3 V or 5 V V
ref(B)
1.8 V V
ref(A)
and 3.3 V or 5 V V
ref(B)
2.5 V V
ref(A)
and 5 V V
ref(B)
3.3 V V
ref(A)
and 5 V V
ref(B)
NVT2001; NVT2002
Bidirectional voltage level translator for open-drain and
push-pull applications
Rev. 4 — 27 January 2014 Product data sheet
NVT2001_NVT2002 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 27 January 2014 2 of 26
NXP Semiconductors
NVT2001; NVT2002
Bidirectional voltage level translator
Low 3.5 ON-state connection between input and output ports provides less signal
distortion
5 V tolerant I/O ports to support mixed-mode signal operation
High-impedance An and Bn pins for EN = LOW
Lock-up free operation
Flow through pinout for ease of printed-circuit board trace routing
ESD protection exceeds 4 kV HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
3. Ordering information
[1] GTL2002 = NVT2002.
[2] ‘X’ will change based on date code.
3.1 Ordering options
Table 1. Ordering information
T
amb
=
40
C to +85
C.
Type number Topside
marking
Number
of bits
Package
Name Description Version
NVT2002DP
[1]
N2002 2 TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm
SOT505-1
NVT2002GD
[1]
N02 2 XSON8U plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 2 0.5 mm
SOT996-2
NVT2001GM N1X
[2]
1 XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 1.45 0.5 mm
SOT886
Table 2. Ordering options
Type number Orderable
part number
Package Packing method Minimum
order
quantity
Temperature
NVT2002DP NVT2002DP,118 TSSOP8 Reel 13” Q1/T1
*Standard mark SMD
2500 T
amb
= 40 C to +85 C
NVT2002GD NVT2002GD,125 XSON8U Reel 7” Q3/T4
*Standard mark
3000 T
amb
= 40 C to +85 C
NVT2001GM NVT2001GM,115 XSON6 Reel 7” Q1/T1
*Standard mark SMD
5000 T
amb
= 40 C to +85 C
NVT2001_NVT2002 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 27 January 2014 3 of 26
NXP Semiconductors
NVT2001; NVT2002
Bidirectional voltage level translator
4. Functional diagram
5. Pinning information
5.1 Pinning
5.1.1 1-bit in XSON6 package
5.1.2 2-bit in TSSOP8 and XSON8U packages
Fig 1. Logic diagram of NVT2001; NVT2002 (positive logic)
002aae132
A1
An
VREFA
GND
VREFB
B1
Bn
EN
SW
SW
NVT20xx
Fig 2. Pin configuration for XSON6
NVT2001GM
VREFA
002aae211
GND
A1
VREFB
EN
B1
Transparent top view
2
3
1
5
4
6
Fig 3. Pin configuration for TSSOP8 Fig 4. Pin configuration for XSON8U
NVT2002DP
GND EN
VREFA VREFB
A1 B1
A2 B2
002aae214
1
2
3
4
6
5
8
7
002aae215
NVT2002GD
Transparent top view
8
7
6
5
1
2
3
4
GND
VREFA
A1
A2
EN
VREFB
B1
B2

NVT2002GD,125

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Translation - Voltage Levels BIDIRCTIONL VOLT-LVL TRANSL O-DRN P-P APP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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