FEMTOCLOCK™ CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
844008I-15 DATA SHEET
8 REVISION B 7/2/15
CRYSTAL INPUT INTERFACE
The 844008I-15 has been characterized with an 18pF
parallel resonant crystals. The capacitor values shown in
FIGURE 2. CRYSTAL INPUt INTERFACE
Figure 2 below were determined using a 25MHz parallel
resonant crystal and were chosen to minimize the ppm error.
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The 844008I-15 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. V
DD
and V
DDA
should be individually connected
to the power supply plane through vias, and bypass capacitors
should be used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how a 10Ω
resistor along with a 10µF and a 0.01μF bypass capacitor should
be connected to each V
DDA
.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10Ω
V
DDA
10μF
.01μF
3.3V
.01μF
V
DD
INPUTS:
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVDS
All unused LVDS outputs should be terminated with 100Ω resistor
between the differential pair.
