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XC6119C11ANR-G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
7/16
XC6119
Series
A typical circuit example is shown in Figure 1, and the timing chart of Figure 1 is shown in Figure 2 on the next page.
① As an early state, the input voltage pin is applied sufficiently high voltage to the release voltage and the delay capacitance
(Cd) is charged to the input pin voltage. While the input pin voltage (V
IN
) starts dropping to reach the detect voltage (V
DF
)
(V
IN
> V
DF
), the output voltage (V
OUT
) keeps the “High” level (=V
IN
).
② When the input pin voltage keeps dropping and becomes equal to the detect voltage (V
IN
= V
DF
), an N-ch transistor for the
delay capacitance discharge is turned ON, and starts to discharge the delay capacitance. For the internal circuit, which
uses the delay capacitance pin as power input, the reference voltage operates as a comparator of VIN, and the output
voltage changes into the “Low” level (≦V
IN
×0.1). The detect delay time (t
DF
) is defined as time which ranges from V
IN
=V
DF
to the V
OUT
of “Low” level (especially, when the Cd pin is not connected: t
DF0
).
③ While the input pin voltage keeps below the detect voltage, and 0.7V or more, the delay capacitance is discharged to the
ground voltage (=V
SS
) level. Then, the output voltage (V
OUT
) maintains the “Low” level.
④ While the input pin voltage drops to less than 0.7V and it increases again to 0.7V or more, the output voltage may not be able
to maintain the “Low” level. Such an operation is called “Unspecified Operation”, and voltage which occurs at the output pin
voltage is defined as unstable operating voltage (V
UNS
).
■OPERATIONAL EXPLANATION
Figure 1: Typical application circuit example
Figure 2: The timing chart of Figure 1
The circuit which uses the delay
Capacitance pin as power input.
N-ch transictor for the delay
Capacitance discharge.
Delay Capacitor
Input Voltage: V
IN
Delay Capacitance Pin Voltage: V
CD
Release Voltage: V
DF
+V
HYS
Delay Capacitance Pin Threshold Voltage: V
TCD
Detect Voltage: V
DF
Output Pin Voltage: V
OUT
Minimum Operationg Voltage (0.7V)
8/16
XC6119 Series
⑤ While the input pin voltage increases more than 0.7V and it reaches to the release voltage level (V
IN
＜V
DF
+V
HYS
), the
output voltage (V
OUT
) maintains the “Low” level.
⑥ When the input pin voltage continues to increase more than 0.7V up to the release voltage level (= V
DF
+ V
HYS
), the N-ch
transistor for the delay capacitance discharge will be turned OFF, and the delay capacitance will be started discharging via a
delay resistor (
R
DELAY
). The internal circuit, which uses the delay capacitance pin as power input, will operate as a
hysteresis comparator (Rise Logic Threshold: V
TLH
=V
TCD
, Fall Logic Threshold: V
THL
=V
SS
) while the input pin voltage keeps
higher than the detect voltage (V
IN
> V
DF
).
⑦ While the input pin voltage becomes equal to the release voltage or higher and keeps the detect voltage or higher, the delay
capacitance (Cd) will be charged up to the input pin voltage. When the delay capacitance pin voltage (V
CD
) reaches to the
delay capacitance pin threshold voltage (V
TCD
), the output voltage changes into the “High” (=V
IN
) level. t
DR
is defined as
time which ranges from V
IN
=V
DF
+V
HYS
to the V
OUT
of “High” level (especially when the Cd pin is not connected: t
DR0
). t
DR
can be given by the formula (1).
t
DR
=
－
R
DELAY
×
Cd
×
In (1
－
VTCD / VIN) +t
DR0
…(1)
* In = a natural logarithm
The release delay time can also be briefly calculated with the formula (2) because the delay resistance is 2.0MΩ(TYP.) and the
delay capacitance pin threshold voltage is VIN /2 (TYP.)
t
DR
=R
DELAY
×
Cd
×
0.69
…
(2)
* R
DELAY
is 2.0MΩ(TYP.)
As an example, presuming that the delay capacitance is 0.68μF, t
DR
is :
2.0
×
10
6
×
0.68
×
10
-6
×
0.69=938(ms)
* Note that the release delay time may remarkably be short when the delay capacitance is not discharged to the ground (=V
SS
)
level because time described in ③ is short.
⑧ While the input pin voltage is higher than the detect voltage (V
IN
> V
DF
), therefore, the output voltage maintains the
“High”(=V
IN
) level.
●Release Delay Time Chart
Delay Capacitance [Cd]
(μF)
Release Delay Time [tDR] (TYP.)
(ms)
Release Delay Time [tDR] (MIN. ~ MAX.) *1
(ms)
0.01 13.8 11.0 ~ 16.6
0.022 30.4 24.3 ~ 36.4
0.047 64.9 51.9 ~ 77.8
0.1 138 110 ~ 166
0.22 304 243 ~ 364
0.47 649 519 ~ 778
1 1380 1100 ~ 1660
* The release delay time values above are calculate by using formula (2).
*1: The release delay time (t
DR
) is influenced by the release capacitance (Cd).
■OPERATIONAL EXPLANATION
Continued
9/16
XC6119
Series
■NOTES ON USE
Figure 3: Circuit example with the delay capacitance pin (Cd)
connected to a schottky barrier diode
1. Please use this IC within the stated maximum ratings. For temporary, transitional voltage drop or voltage rising
phenomenon, the IC is liable to malfunction should the ratings be exceeded.
2. The input pin voltage drops by the resistance between power supply and the V
IN pin, and by through current at operation of
the IC. At this time, the operation may be wrong if the input pin voltage falls below the minimum operating voltage range.
In CMOS output, for output current, drops in the input pin voltage similarly occur. Oscillation of the circuit may occur if the
drops in voltage, which caused by through current at operation of the IC, exceed the hysteresis voltage. Note it especially
when you use the IC with the V
IN pin connected to a resistor.
3. Note that a rapid and high fluctuation of the input pin voltage may cause a wrong operation.
4. Power supply noise may cause an operational function error. Care must be taken to put an external capacitor between
V
IN
-GND and test on the board carefully.
5. When there is a possibility of which the input pin voltage falls rapidly (e.g.: 6.0V to 0V) at release operation with the delay
capacitance pin (Cd) connected to a capacitor, use a schottky barrier diode connected between the V
IN pin and the Cd pin
as the Figure 3 shown below.
6. When N-channel open drain output is used, output voltages V
OUT
at voltage detection and release are determined by a
pull-up resistor tied to the output pin. A resistance value of the pull-up resistor can be selected with referring to the
followings. (Refer to Figure 4)
During detection, the formula is given as
V
OUT
=V
PULL
/(1+R
PULL
/R
ON
)
where V
PULL
is pull-up voltage and R
ON
(*1) is ON resistance of N-channel driver M5 (R
ON
=V
DS
/I
OUT1
from the electrical
characteristics table).
For example, when V
IN
=2.0V (*2), R
ON
= 0.5/0.8×10
-3
=625Ω(MIN.) and if you want to get V
OUT
less than 0.1V when
V
PULL
=3.0V, R
PULL
can be calculated as follows;
R
PULL
=(V
PULL
/V
OUT
-1)×R
ON
=(3/0.1-1)×625≒18ｋΩ
Therefore, pull-up resistance should be selected 18kΩ or higher.
(*1) V
IN
is smaller, R
ON
is bigger
(*2) For the calculation, the lowest V
IN
should be used among of the V
IN
range
During release, the formula is given as
V
OUT
=V
PULL
/(1+R
PULL
/R
OFF
)
where V
PULL
is pull-up voltage R
OFF
is OFF resistance of N-channel driver M5 (R
OFF
=V
OUT
/I
LEAK
=15MΩ from the
electrical characteristics table)
For examples, if you want to get V
OUT
larger than 5.99V when V
PULL
is 6.0V, R
PULL
can be calculated as follows;
R
PULL
=(V
PULL
/V
OUT
-1)×R
OFF
=(6/5.99-1)×15×10
6
≒25kΩ
Therefore, pull-up resistance should be selected 25kΩ or below.
7. Torex places an importance on improving our products and their reliability. We request that users incorporate fail-safe
designs and post-aging protection treatment when using Torex products in their systems.
Note: R
OFF
=V
OUT
/I
LEAK
Figure 4: Circuit example of XC6109N Series
(No resistor needed for
CMOS output products)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

XC6119C11ANR-G

Mfr. #:
Buy XC6119C11ANR-G
Manufacturer:
Torex Semiconductor
Description:
Supervisory Circuits Voltage Detector with Delay Cap. Pin
Lifecycle:
New from this manufacturer.
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