10
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
WUU
U
A 5.1k resistor is tied from the FB pin to V
OUTLO
, setting the
internal threshold to about 2.9V. The new reset threshold
voltage is set by the external resistive divider connected to
COMP2. When V
OUTLO
drops below the new threshold,
COMPOUT pulls FB to ground, changing the internal
threshold at COMP1 to 5.88V and generating a reset.
Finally, the comparator may be used to monitor a negative
supply as shown in Figure 8e. The external resistor divider
Figure 8c shows how the comparator can be used to
generate a reset when the 12V supply (V
OUTHI
) drops
below 10.8V. The 5V supply (V
OUTLO
) also generates a
reset when it dips below 4.65V. When the 12V supply
drops below 10.8V, COMPOUT will pull the FB pin low
setting the internal threshold voltage for comparator 1 to
5.88V. Since V
OUTLO
is less than 5.88V, PWRGD immedi-
ately goes low and a reset is generated 32µs later.
Figure 8d shows how the comparator can be used to
override the internal reset voltage for a 5V supply on
V
OUTLO
.
+
+
V
CCLO
V
CCLO
1421 F08c
1.232V
LTC1421
20µA
20µA
8
14
13
15
11
16
20
26.7k
COMP1
COMP2
RESET
TIMING
73.5k
107k
1%
13.7k
1%
6
7
71.5k
5V 12V
Figure 8c. Reset 12V at 10.8V, Reset 5V at 4.65V Figure 8e. Monitor –12V at –10.8V, Reset 5V at 4.65V
+
+
V
CCLO
V
CCLO
1421 F08e
1.232V
LTC1421
20µA
20µA
8
14
13
15
11
16
20
26.7k
COMP1
COMP2
RESET
TIMING
73.5k
107k
1%
10k
5%
13.7k
1%
6
7
71.5k
5V
12V
12V
Figure 8d. Reset 5V at 4.5V
+
+
V
CCLO
V
CCLO
1421 F08d
1.232V
LTC1421
20µA
20µA
8
14
13
15
11
16
20
26.7k
COMP1
COMP2
RESET
TIMING
73.5k
102k
1%
5.1k
5%
38.3k
1%
6
7
71.5k
5V
12V
+
+
V
CCLO
V
CCLO
1421 F08b
1.232V
LTC1421
20µA
20µA
8
14
13
15
11
16
20
26.7k
COMP1
COMP2
RESET
TIMING
73.5k
10k
5%
107k
1%
38.3k
1%
6
7
71.5k
3.3V 5V
Figure 8b. Monitor 5V, Reset 3.3V at 2.9V
11
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
WUU
U
is connected between REF (Pin 8) and the negative supply
and the trip point of Comparator 2 set to GND.
Soft Reset Generation
A soft reset that doesn’t cycle the supply voltage can be
generated externally using Pin 11 (FB) as shown in Figure
9. For a 5V supply the FB pin is left floating to set the
internal supply monitor trip voltage to 4.65V. However, if
the FB pin is pulled to ground for more than 32µs via a push
button or open-collector logic gate, the internal trip point
will go to 5.88V and the RESET pin will pull low. RESET will
remain low for 200ms after the FB pin is released. The
RESET signal will also be pulled low when the voltage at
the V
OUTLO
pin dips below 4.65V for more than 32µs.
When using a 3.3V supply, a 1k resistor must be con-
nected from the FB pin to V
CCLO
to set the internal trip point
to 2.90V.
sense resistor is greater than 50mV for more than 20µs.
When the circuit breaker trips, both N-channel MOSFETs
are quickly turned off, FAULT and PWRGD go low and
RESET is pulled low 32µs later. FAULT can be connected
to a LED or a logic signal back to the host to indicate a faulty
board. The chip will remain in the tripped state until a
power-on reset is generated, or the power on V
CCHI
and
V
CCLO
is cycled. If the circuit breaker feature is not used,
short V
CCLO
to SETLO and V
CCHI
to SETHI.
If more than 20µs of response time is needed to reject
supply noise, an external resistor and capacitor can be
added to the sense circuit as shown in Figure 10.
Figure 9. Generating a Soft Reset
Undervoltage Lockout
On power-up, an undervoltage lockout circuit prevents the
GATELO and GATEHI charge pumps from turning on until
V
CCLO
and V
CCHI
have both exceeded 2.45V.
Electronic Circuit Breaker
The LTC1421 features an electronic circuit breaker func-
tion that protects against short circuits or excessive cur-
rents on the supplies. By placing a sense resistor between
the supply input and set pin of either supply, the circuit
breaker will be tripped whenever the voltage across the
LTC1421
3.3V
5V
1/6 LS7404
OPEN
COLLECTOR
GND
32µs
200ms
FB
11 7
12
1421 F09
R1
1k
R1 USED FOR 3.3V
SUPPLY ONLY
RESET
RESET
FB
RESET
LOGIC
23
R
SENSE
C
F
Q1
22
R
F
21 20
V
CCLO
SETLO GATELO V
OUTLO
LTC1421
1421 F10
43
21
Figure 10. Short-Circuit Protection Circuit
Figure 11. AUXV
CC
Circuitry
GATE DRIVE
CIRCUITRY
10k
1µF
AUXV
CC
1421 F11
V
CCLO
24
LTC1421
23
GATELO GATEHI
21 17
Auxiliary V
CC
When a short circuit occurs on the board, it is possible to
draw enough current to cause the backplane supply
voltage to collapse. If the input supply voltage collapses to
a low enough voltage and the LTC1421 gate drive circuitry
is unable to shut off the N-channel pass transistors, the
system might freeze up in a permanent short condition.
To prevent this from occurring, the gate discharge cir-
cuitry inside the LTC1421 is powered from AUXV
CC
,
which is in turn powered from V
CCLO
through an internal
Schottky diode and current limiting resistor (Figure 11).
12
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
WUU
U
When V
CCLO
collapses, there is enough energy stored on
the 1µF capacitor connected to AUXV
CC
to keep the gate
discharge circuitry alive long enough to fully turn off the
external N-channels.
Power N-Channel Selection
The R
DS(ON)
of the external pass transistor must be low
enough so that the voltage drop across it is about 200mV
or less at full current. If the R
DS(ON)
is too high, the voltage
drop across the transistor might cause the output voltage
to trip the reset circuit. Table 2 lists the transistors that are
recommended for use with the LTC1421.
Table 2. N-Channel Selection Guide
CURRENT PART
LEVEL (A) NUMBER MANUFACTURER DESCRIPTION
0 to 1 MMDF2N02E ON Semiconductor Dual N-Channel SO-8
R
DS(ON)
= 0.1
1 to 2 MMDF3NO2HD ON Semiconductor Dual N-Channel SO-8
R
DS(ON)
= 0.09
2 to 5 MTB30N06 ON Semiconductor Single 30A
N-Channel DD Pak
R
DS(ON)
= 0.05
5 to 10 MTB50N06E ON Semiconductor Single
N-Channel DD Pak
R
DS(ON)
= 0.025
10 to 20 MTB75N05HD ON Semiconductor Single
N-Channel DD Pak
R
DS(ON)
= 0.0095
Data Bus
When a board is inserted or removed from the host, care
must be given to prevent the system data bus from being
corrupted when the data pins make or break contact. One
problem is that the fully discharged input or output capaci-
tance of the logic gates on the board will draw an inrush
current when the data bus pins first make contact. The
inrush current can temporarily corrupt the data bus, but
usually will not cause long term damage. The problem can
be minimized by insuring the input or output data bus
capacitance is kept as small as possible.
The second, and more serious problem involves the
diodes to V
CC
at the input and output of most logic families
(Figure 12).
V
CC
OUT
BACKPLANE BOARD
D1
D2
1421 F12
DATA
BUS
CONNECTOR
Figure 12. Typical Logic Gate Loading the Data Bus
Figure 13: Buffering the Data Bus
+
21 20
C
LOAD
2223
5
12
24
3
14
4
17
7
18
8
21
11
22
12
2
15
5
16
6
SYSTEM
DATA BUS
BOARD
DATA BUS19
9
20
10
23
1
13
QS3384
V
CC
GND
1421 F13
V
CC
5V
CONNECTOR
LTC1421
R1
0.005
Q1
MTB50N06E
GNDDISABLE
43
21
With the board initially unpowered, the V
CC
input to the
logic gate is at ground potential. When the data bus pins
make contact, the bus line is clamped to ground through
the input diode D1 to V
CC
. Large amounts of current can
flow through the diode and cause the logic gate to latch up
and destroy itself when the power is finally applied. This

LTC1421CG#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Hot Swap Cntr
Lifecycle:
New from this manufacturer.
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