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LTC1421ISW#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
4
LTC1421/LTC1421-2.5
TYPICAL PERFORMANCE CHARACTERISTICS
U
W
TEMPERATURE (°C)
–50
1.232
1.234
1.238
25 75
1421 G01
1.230
1.228
–25 0
50 100 125
1.226
1.224
1.236
REFERENCE VOLTAGE (V)
V
CCLO
= 5V
V
CCHI
= 12V
Reference Voltage vs
Temperature
SOURCE CURRENT (mA)
0
REFERENCE VOLTAGE (V)
1.235
1.240
1.245
8
1421 G03
1.230
1.225
1.220
2
4
6
10
V
CCLO
= 5V
V
CCHI
= 12V
Reference Voltage
vs Source CurrentGate Voltage vs Temperature
TEMPERATURE (°C)
–50
21
22
24
25 75
1421 G02
20
19
–25 0
50 100 125
18
17
23
GATE VOLTAGE (V)
V
CCLO
= 5V
V
CCHI
= 12V
GATEHI
GATELO
GATELO Voltage vs V
CCLO
Voltage
V
CCLO
VOLTAGE (V)
0
20
22
26
610
1421 G04
18
16
24
81214
14
12
24
GATELO VOLTAGE (V)
V
CCHI
= 12V
GATEHI Voltage vs V
CCHI
Voltage
V
CCHI
VOLTAGE (V)
0
20
22
26
610
1421 G05
18
16
24
81214
14
12
24
GATEHI VOLTAGE (V)
V
CCLO
= 5V
I
CCLO
Supply Current
vs Temperature
TEMPERATURE (°C)
–50
1400
25 75
1421 G06
1300
–25 0
50 100 125
1200
1500
I
CCLO
SUPPLY CURRENT (µA)
V
CCLO
= 5V
V
CCHI
= 12V
V
OL
vs I
SINK
CPON Voltage vs Sink Current
(Charge Pump Off)
I
CCHI
Supply Current
vs Temperature
TEMPERATURE (°C)
–50
540
25 75
1421 G07
530
–25 0
50 100 125
520
550
545
535
525
555
I
CCHI
SUPPLY CURRENT (µA)
V
CCLO
= 5V
V
CCHI
= 12V
SINK CURRENT (mA)
0
0
VOLTAGE (mV)
100
200
300
400
500
FAULT
600
2468
1421 G08
10
V
CCLO
= 5V
V
CCHI
= 12V
COMPOUT
PWRGD
RESET
SINK CURRENT (mA)
0
0
CPON VOLTAGE (V)
0.5
1.0
1.5
2.0
2.5
0.5
1.0 1.5 2.0
1421 G09
2.5 3.0
V
CCLO
= 5V
V
CCHI
= 12V
5
LTC1421/LTC1421-2.5
TYPICAL PERFORMANCE CHARACTERISTICS
U
W
CPON Voltage vs Source Current
(Charge Pump On)
SOURCE CURRENT (mA)
0
0
CPON VOLTAGE (V)
1
2
3
4
5
–0.5
–1.0 –1.5 –2.0
1421 G10
–2.5 –3.0
V
CCLO
= 5V
V
CCHI
= 12V
I
CCLO
Supply Current
vs V
CCLO
Voltage
V
CCLO
VOLTAGE (V)
0
4
5
7
610
1421 G11
3
2
24
81214
1
0
6
I
CCLO
SUPPLY CURRENT (mA)
V
CCHI
= 12V
PIN FUNCTIONS
UUU
CON1 (Pin 1): TTL Level Input with a Pull-Up to V
CCLO
.
Together with CON2, it is used to indicate board connec-
tion. The pin must be tied to ground on the host side of the
connector. When using staggered connector pins, CON1
and CON2 must be the shortest and must be placed at
opposite corners of the connector. Board insertion is
assumed after CON1 and CON2 are both held low for 20ms
after power-up.
CON2 (Pin 2):
TTL Level Input with a Pull-Up to V
CCLO
.
Together with CON1 it is used to indicate board connec-
tion.
POR (Pin 3): TTL Level Input with a Pull-Up to V
CCLO
.
When the pin is pulled low for at least 20ms, a hard reset
is generated. Both V
OUTLO
and V
OUTHI
will turn off at a
controlled rate. A power-up sequence will not start until
the POR pin is pulled high. If POR is pulled high before
V
OUTLO
and V
OUTHI
are fully discharged, a power-up
sequence will not begin until the voltage at V
OUTLO
and
V
OUTHI
are below V
TRIP
. The electronic circuit breaker will
be reset by pulling POR low.
FAULT (Pin 4): Open Drain Output to GND with a Weak
Pull-Up to V
CCLO
. The pin is pulled low when an overcur-
rent fault is detected at V
OUTLO
or V
OUTHI
.
DISABLE (Pin 5): CMOS Output. The signal is used to
disable the board’s data bus during insertion or removal.
PWRGD (Pin 6): Open Drain Output to GND with a Weak
Pull-Up to V
CCLO
. The pin is pulled low immediately after
V
OUTLO
falls below its reset threshold voltage. The pin is
pulled high immediately after V
OUTLO
rises above its reset
threshold voltage.
RESET (Pin 7):
Open Drain Output to GND with a Weak
Pull-Up to V
CCLO
. The pin is pulled low when a reset
condition is detected. A reset will be generated when any
of the following conditions are met: Either CON1 or CON2
is high, POR is pulled low, V
CCLO
or V
CCHI
are below their
respective undervoltage lockout thresholds, PWRGD goes
low or an overcurrent fault is detected at V
OUTLO
or
V
OUTHI
. RESET will go high 200ms after PWRGD goes
high. On power failure, RESET will go low 32µs after
PWRGD goes low.
REF (Pin 8): The Reference Voltage Output. V
OUT
= 1.232V
±1%. The reference can source up to 5mA of current. A
1µF bypass capacitor is recommended.
CPON (Pin 9): CMOS Output That Can Be Pulled Below
Ground. CPON is pulled high when the internal charge
pumps for GATELO and GATEHI are turned on. CPON is
pulled low when the charge pumps are turned off. The pin
can be used to control an external MOSFET for a –5V to
–12V supply.
6
LTC1421/LTC1421-2.5
PIN FUNCTIONS
UUU
RAMP (Pin 10): Analog Power-Up Ramp Control Pin. By
connecting an external capacitor between the RAMP and
GATEHI, a positive linear voltage ramp on GATEHI and
GATELO is generated on power-up with a slope equal to
20µA/C
RAMP
. A 10k resistor in series with the capacitor
enhances the ESD performance at the GATEHI pin.
FB (Pin 11): Analog Feedback Input. FB is used to set the
reset threshold voltage on V
CCLO
. For a 5V supply leave FB
floating. For a 3.3V supply, short FB to V
CCLO
.
GND (Pin 12): Ground
COMP
+
(Pin 13): Noninverting Comparator Input.
COMP
–
(Pin 14): Inverting Comparator Input.
COMPOUT (Pin 15): Open Drain Comparator Output.
V
OUTHI
(Pin 16): High Supply Voltage Output. This must be
the higher of the two supply voltage outputs.
GATEHI (Pin 17): The High Side Gate Drive for the High
Supply N-Channel. An internal charge pump guarantees at
least 6V of gate drive. The slope of the voltage rise at
GATEHI is set by the external capacitor connected between
GATEHI and RAMP. When the circuit breaker trips, GATEHI
is immediately pulled to GND.
SETHI (Pin 18): The Circuit Breaker Set Pin for the High
Supply. With a sense resistor placed in the supply path
between V
CCHI
and SETHI, the circuit breaker will trip when
the voltage across the resistor exceeds 50mV for more
than 20µs. To disable the circuit breaker, V
CCHI
and SETHI
should be shorted together.
V
CCHI
(Pin 19): The Positive Supply Input. This must be the
higher of the two input supply voltages. An undervoltage
lockout circuit disables the chip until the voltage at V
CCHI
is greater than 2.45V.
V
OUTLO
(Pin 20): Low Supply Voltage Output. This must be
the lower of the two supply voltage outputs.
GATELO (Pin 21): The High Side Gate Drive for the Low
Supply N-Channel Pass Transistor. An internal charge
pump guarantees at least 10V of gate drive. The slope of
the voltage rise at GATELO is set by the external capacitor
connected between GATEHI and RAMP. When the circuit
breaker trips GATELO is immediately pulled to GND.
SETLO (Pin 22): The Circuit Breaker Set Pin for the Low
Supply. With a sense resistor placed in the supply path
between V
CCLO
and SETLO, the circuit breaker will trip
when the voltage across the resistor exceeds 50mV for
more than 20µs. To disable the circuit breaker, V
CCLO
and
SETLO should be shorted together.
V
CCLO
(Pin 23): The Positive Supply Input. V
CCLO
must be
equal to or lower voltage than V
CCHI
. An undervoltage
lockout circuit disables the chip until the voltage at V
CCLO
is greater than 2.45V.
AUXV
CC
(Pin 24): The supply input for the GATELO and
GATEHI discharge circuitry. Connect a 1µF capacitor to
ground. AUXV
CC
is powered from V
CCLO
via an internal
Schottky diode and series resistor.
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LTC1421ISW#PBF

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Manufacturer:
Analog Devices Inc.
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