Document Number: 38-02018 Rev. *E Page 10 of 16
Switching Characteristics
Over the Operating Range
Parameter Description Min Max Unit
f
REF
Reference Frequency MODE = LOW 6.41 6.55 MHz
MODE = HIGH 19.24 19.64 MHz
f
B
Bit Time
[8]
MODE = LOW 19.5 19.1 ns
MODE = HIGH 6.50 6.40 ns
t
ODC
Output Duty Cycle (TCLK, RCLK)
[9]
48 52 %
t
RF
Output Rise/Fall Time
[9]
0.4 1.2 ns
t
LOCK
PLL Lock Time (RIN transition density 25%)
[10]
–3ms
t
RPWH
REFCLK Pulse Width HIGH 10 – ns
t
RPWL
REFCLK Pulse Width LOW 10 – ns
t
DV
Data Valid 3–ns
t
DH
Data Hold 1–ns
t
PD
Propagation Delay (RIN to ROUT, TSER to TOUT)
[11]
–10ns
Jitter
Generation
Jitter Generation of RX PLL – 0.01
UIrms
f
3dB
3 dB Gain Bandwidth of RX PLL (Jitter Transfer
Bandwidth)
At 155 MHz – 130 kHz
f
3dB
3 dB Gain Bandwidth of RX PLL (Jitter Transfer
Bandwidth)
At 52 MHz – 40 kHz
Gpeak Maximum Peaking of RX PLL
[12]
–0.1dB
Notes
8. f
B
is calculated a 1/(f
REF8
).
9. Tested initially and after any design or process changes that may affect these parameters.
10. t
LOCK
is the time needed for transitioning from lock to REFCLK × 8 to lock to data.
11. The ECL switching threshold is the differential zero crossing (i.e., the place where + and – signals cross).
12. Maximum Peaking is measured using a maximum of 1.2 ns peak to peak duty cycle distortion for RIN
and applying sinusoidal jitter to the input signal at the maximum
amplitude of the jitter tolerance mask for each specific jitter frequency as specified by the Bellcore GR-253-Core issue 2, Dec 1995 - SONET Common Generic
Criteria for OC-3.
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