7
LT1185
1185ff
Large output capacitors (electrolytic or solid tantalum)
will not cause the LT1185 to oscillate, but they will cause
a damped “ringing” at light load currents where the ESR
of the capacitor is several orders of magnitude lower than
the load resistance. This ringing only occurs as a result of
transient load or line conditions and normally causes no
problems because of its low amplitude ( 25mV).
Heat Sinking
The LT1185 will normally be used with a heat sink. The size
of the heat sink is determined by load current, input and
output voltage, ambient temperature, and the thermal
resistance of the regulator, junction-to-case (θ
JC
). The
LT1185 has two separate values for θ
JC
: one for the power
transistor section, and a second, lower value for the
control section. The reason for two values is that the
power transistor is capable of operating at higher continu-
ous temperature than the control circuitry. At low power
levels, the two areas are at nearly the same temperature,
and maximum temperature is limited by the control area.
At high power levels, the power transistor will be at a
significantly higher temperature than the control area
and its maximum operating temperature will be the
limiting factor.
To calculate heat sink requirements, you must solve a
thermal resistance formula twice, one for the power
transistor and one for the control area. The
lowest
value
obtained for heat sink thermal resistance must be used. In
these equations, two values for maximum junction tem-
perature and junction-to-case thermal resistance are used,
as given in Electrical Specifications.
Example: A commercial version of the LT1185 in the
TO-220 package is to be used with a maximum ambient
temperature of 60°C. Output voltage is 5V at 2A. Input
voltage can vary from 6V to 10V. Assume an interface
resistance of 1°C/W.
First solve for control area, where the maximum junction
temperature is 125°C for the TO-220 package, and
θ
JC
= 1°C/W:
Next, solve for power transistor limitation, with
T
JMAX
= 150°C, θ
JC
= 3°C/W:
The lowest number must be used, so heat sink resistance
must be less than 4.2°C/W.
Some heat sink data sheets show graphs of heat sink
temperature rise vs power dissipation instead of listing a
value for thermal resistance. The formula for θ
HS
can be
rearranged to solve for maximum heat sink temperature
rise:
T
HS
= T
JMAX
– T
AMAX
– P(θ
JC
+ θ
CHS
)
Using numbers from the previous example:
T
HS
= 125°C – 60 – 10.5(1 + 1) = 44°C control
section
T
HS
= 150°C – 60 – 10.5(3 + 1) = 48°C power
transistor
The smallest rise must be used, so heat sink temperature
rise must be less than 44°C at a power level of 10.5W.
For board level applications, where heat sink size may be
critical, one is often tempted to use a heat sink which
barely meets the requirements. This is permissible
if
correct assumptions were made concerning maximum
ambient temperature and power levels. One complicating
P = (10V – 5V) (2A) +
2A
40
(10V) = 10.5W
θ
HS
=
125°C – 60°C
10.5W
– 1°C/W – 1°C/W = 4.2°C/W
θ
HS
=
150 – 60
10.5
– 3 – 1 = 4.6°C/W
θ
HS
=
(T
JMAX
– T
AMAX
)
P
θ
JC
θ
CHS
.
θ
HS
= Maximum heat sink thermal resistance
θ
JC
= LT1185 junction-to-case thermal resistance
θ
CHS
= Case-to-heat sink (interface) thermal
resistance, including any insulating washers
T
JMAX
= LT1185 maximum operating junction
temperature
T
AMAX
= Maximum ambient temperature in
customers application
P = Device dissipaton
= (V
IN
– V
OUT
) (I
OUT
) +
I
OUT
40
(V
IN
)
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8
LT1185
1185ff
factor is that local ambient temperature may be somewhat
higher because of the point source of heat. The conse-
quences of excess junction temperature include poor
reliability, especially for plastic packages, and the possi-
bility of thermal shutdown or degraded electrical charac-
teristics. The final design should be checked
in situ
with a
thermocouple attached to the regulator case under worst-
case conditions of high ambient, high input voltage and
full load.
What About Overloads?
IC regulators with thermal shutdown, like the LT1185,
allow heat sink designs which concentrate on worst-case
“normal” conditions and ignore “fault” conditions. An
output overload or short may force the regulator to exceed
its maximum junction temperature rating, but thermal
shutdown is designed to prevent regulator failure under
these conditions. A word of caution however; thermal
shutdown temperatures are typically 175°C in the control
portion of the die and 180°C to 225°C in the power
transistor section. Extended operation at these tempera-
tures can cause permanent degradation of plastic encap-
sulation. Designs which may be subjected to extended
periods of overload should either use the hermetic TO-3
package or increase heat sink size. Foldback current
limiting can be implemented to minimize power levels
under fault conditions.
External Current Limit
The LT1185 requires a resistor to set current limit. The
value of this resistor is 15k divided by the desired current
limit (in amps). The resistor for 2A current limit would be
15k/2A = 7.5k. Tolerance over temperature is ±10%, so
current limit is normally set 15% above maximum load
current. Foldback limiting can be employed if short-circuit
current must be lower than full load current (see Typical
Applications).
The LT1185 has internal current limiting which will over-
ride external current limit if power in the pass transistor
is excessive. The internal limit is 3.6A with a foldback
characteristic which is dependent on input-output volt-
age, not output voltage
per se
(see Typical Performace
Characteristics)
.
Ground Pin Current
Ground pin current for the LT1185 is approximately 2mA
plus I
OUT
/40. At I
OUT
= 3A, ground pin current is typically
2mA + 3/40 = 77mA. Worst case guarantees on the ratio of
I
OUT
to ground pin current are contained in the Electrical
Specifications.
Ground pin current can be important for two reasons. It
adds to power dissipation in the regulator and it can affect
load/line regulation if a long line is run from the ground pin
to load ground. The additional power dissipation is found
by multiplying ground pin current by input voltage. In a
typical example, with V
IN
= 8V, V
OUT
= 5V and I
OUT
= 2A, the
LT1185 will dissipate (8V – 5V)(2A) = 6W in the pass
transistor and (2A/40)(8V) = 0.4W in the internal drive
circuitry. This is only a 1.5% efficiency loss, and a 6.7%
increase in regulator power dissipation, but these values
will increase at higher output voltages.
Ground pin current can affect regulation as shown in
Figure 2. Parasitic resistance in the ground pin lead will
create a voltage drop which
increases
output voltage as
load current is increased. Similarly, output voltage can
decrease
as input voltage increases because the “I
OUT
/40”
component of ground pin current drops significantly at
higher input-output differentials. These effects are small
enough to be ignored for local regulation applications, but
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Figure 2. Proper Connection of Positive Sense Lead
+
R1*
2.37k
R2
REF GND
FB
V
OUT
V
IN
LT1185
R
LIM
+
V
IN
V
OUT
LT1185 • F02
LOAD
PARASITIC
LEAD RESISTANCES
– r
b
+
I
GND
r
a
*R1 SHOULD BE CONNECTED DIRECTLY TO GROUND LEAD, NOT TO THE LOAD,
SO THAT r
a
0. THIS LIMITS THE OUTPUT VOLTAGE ERROR TO (I
GND
)(r
b
).
ERRORS CREATED BY r
a
ARE MULTIPLIED BY (1 + R2/R1). NOTE THAT V
OUT
INCREASES
WITH INCREASING GROUND PIN CURRENT. R2 SHOULD BE CONNECTED
DIRECTLY TO LOAD FOR REMOTE SENSING
9
LT1185
1185ff
APPLICATIO S I FOR ATIO
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Figure 3. Shutdown Techniques
R
LIM
4k
+
V
IN
R6
30k
R7
2.4k
R1
R2
V
OUT
+
Q1
2N3906
*
LT1185 • F3a
*CMOS LOGIC
FOR HIGHER VALUES OF R
LIM
, MAKE R7 = (R
LIM
)(0.6)
5V
R5
300k
+
REF GND
FB
V
OUT
V
IN
LT1185
5V Logic, Positive Regulated Output
5V Logic, Negative Regulated Output
R
LIM
LT1185 • F03b
REF GND
FB
V
OUT
LT1185V
IN
R4
33k
5V
“HI” = OUTPUT “OFF”
3 EA 1N4148
V
IN
Q1
2N3906
for remote sense applications, they may need to be con-
sidered. Ground lead resistance of 0.4 would cause an
output voltage error of up to (3A/40)(0.4) = 30mV, or
0.6% at V
OUT
= 5V. Note that if the sense leads are
connected as shown in Figure 2, with r
a
0, this error is
a fixed number of millivolts, and does not increase as a
function of DC output voltage.
Shutdown Techniques
The LT1185 can be shut down by open-circuiting the REF
pin. The current flowing into this pin must be less than
0.4µA to guarantee shutdown. Figure 3 details several
ways to create the “open” condition, with various logic
levels. For variations on these schemes, simply remember
that the voltage on the REF pin is 2.4V negative with
respect to the ground pin.
Output Overshoot
Very high input voltage slew rate during start-up may
cause the LT1185 output to overshoot. Up to 20% over-
shoot could occur with input voltage ramp-up rate exceed-
ing 1V/µs. This condition cannot occur with normal 50Hz
to 400Hz rectified AC inputs because parasitic resistance
and inductance will limit rate of rise even if the power
switch is closed at the peak of the AC line voltage. This
assumes that the switch is in the AC portion of the circuit.
If instead, a switch is placed directly in the regulator input
so that a large filter capacitor is precharged, fast input slew
rates will occur on switch closure. The output of the
regulator will slew at a rate set by current limit and output
capacitor size; dVdt = I
LIM
/C
OUT
. With I
LIM
= 3.6A and C
OUT
= 2.2µF, the output will slew at 1.6V/µs and overshoot can
occur. This overshoot can be reduced to a few hundred
millivolts or less by increasing the output capacitor to
10µF and/or reducing current limit so that output slew rate
is held below 0.5V/µs.
A second possibility for creating output overshoot is
recovery from an output short. Again, the output slews at
a rate set by current limit and output capacitance. To avoid
overshoot, the ratio I
LIM
/C
OUT
should be less than
0.5 × 10
6
. Remember that load capacitance can be added
to C
OUT
for this calculation. Many loads will have multiple
supply bypass capacitors that total more than C
OUT
.

LT1185IT#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
LDO Voltage Regulators Adj 3A Postive or Negative Low Dropout Regulator
Lifecycle:
New from this manufacturer.
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