8
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT
™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load,
Burst, Deselect and NOOP Cycles
(2)
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
Cycle Address R/W ADV/LD
CE
(1 )
CEN BWx OE
I/O Comments
n A0 H L L L X X X Load read
n+1 X X H X L X X X Burst read
n+2 A1 H L L L X L Q0 Load read
n+3 X X L H L X L Q
0+1
Deselect or STOP
n+4 X X H XLXLQ1NOOP
n+5 A2 H L L L X X Z Load read
n+6 X X H X L X X Z Burst read
n+7 X X L H L X L Q2 Deselect or STOP
n+8 A3 L L LLLLQ
2+1
Load write
n+9 X X H X L L X Z Burst write
n+10 A4 L L L L L X D3 Load write
n+11 X X L H L X X D
3+1
Deselect or STOP
n+12 X X H X L X X D4 NOOP
n+13 A5 L L L L L X Z Load write
n+14 A6 H L L L X X Z Load read
n+15 A7 L L L L L X D5 Load write
n+16 X X H X L L L Q6 Burst write
n+17 A8 H L L L X X D7 Load read
n+18 X X H X L X X D
7+1
Burst read
n+19 A9 L L LLLLQ8Load write
3821 tbl 11