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71V546S100PFGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
6.42
19
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT
™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. Q (A
1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3 etc.
2. CE
2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. When either one of the Chip enables (CE
1, CE2, CE2) is sampled inactive at the rising clock edge, a deselect cycle is initiated. The data-bus tri-states two cycles after the initiation
of the deselect cycle. This allows for any pending data transfers (reads or writes) to be completed.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in two cycles before the actual data is presented to the SRAM.
Timing Waveform of CS Operation
(1,2,3,4)
R
/
W
A
1
C
L
K
A
D
V
/
L
D
A
D
D
R
E
S
S
O
E
D
A
T
A
O
u
t
Q
(
A
1
)
t
C
D
t
C
L
Z
t
C
H
Z
t
C
D
C
t
C
H
t
C
L
t
C
Y
C
t
H
C
t
S
C
t
S
D
t
H
D
A
5
A
3
t
S
B
D
A
T
A
I
n
t
H
E
t
S
E
A
2
t
H
A
t
S
A
A
4
t
H
W
t
S
W
t
H
B
C
E
N
t
H
A
D
V
t
S
A
D
V
3
8
2
1
d
r
w
1
0
Q
(
A
2
)
Q
(
A
3
)
D
(
A
3
)
B
W
1
-
B
W
4
C
E
1
,
C
E
2
(
2
)
20
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT
™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation
(1)
NOTE:
1. A read operation is assumed to be in progress.
Ordering Information
OE
DATA Out
tOHZ
tOLZ
tOE
Valid
3821 drw 1
1
100 pin Plastic Thin Quad Flatpack (PK100-1)
S
Power
XX
Speed
PF
Package
PF
71V546
133
117
100
Clock Frequency in Megahertz
3821 drw 12
Device
Type
PART NUMBER SPEED IN MEGAHERTZt
CD
PARAMETER CLOCK CYCLE TIME
71V546S133PF
71V546S117PF
71V546S100PF
133 MHz
117 MHz
100 MHz
4.2 ns
4.5 ns
5 ns
7.5 ns
8.5 ns
10 ns
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
X
Process/
Temperature
Range
Blank
I
X
Restricted hazardous substance device
G
X
X
Current generation die step optional
First or current generation die step
Blank
100 Thin Quad Flatpack Packaging
6.42
21
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT
™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
6/15/99 Updated to new format
9/13/99 Pg. 12 Corrected ISB3 conditions
Pg. 20 Added Datasheet Document History
12/31/99 Pg. 3, 12, 13, 19 Added Industrial Temperature range offerings
11/22/05 Pg. 3,4 Moved Operating temperature & DC operating tables from page 3 to new page 5. Moved Absolute
rating & Capacitance tables from page 4 to new page 5. Add clarification note to Recommended
Operating Temperature and Absolute Max Ratings tables.
Pg. 20 Updated order information with "Restricted hazardous substance device"
02/23/07 Pg. 20 Added X generation die step to data sheet ordering information.
10/18/08 Pg. 20 Removed "IDT" for orderable part number
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or sramhelp@idt.com
San Jose, CA 95138 408-284-8200 408-284-4532
fax: 408-284-2775
www.idt.com
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

71V546S100PFGI

Mfr. #:
Buy 71V546S100PFGI
Manufacturer:
IDT
Description:
SRAM 128Kx36 ZBT SYNC 3.3V PIPELINED SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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