MC14536B
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7
Figure 2. RC Oscillator Stability Figure 3. RC Oscillator Frequency as a
Function of R
TC
and C
R
S
= 0, f = 10.15 kHz @ V
DD
= 10 V, T
A
= 25°C
R
S
= 120 kW, f = 7.8 kHz @ V
DD
= 10 V, T
A
= 25°C
R
TC
= 56 kW,
C = 1000 pF
V
DD
= 15 V
10 V
5.0 V
8.0
4.0
0
-4.0
-8.0
-12
-16
-55 -25 0 25 50 75 100 125
T
A
, AMBIENT TEMPERATURE (°C)*
*Device Only.
FREQUENCY DEVIATION (%)
TYPICAL RC OSCILLATOR CHARACTERISTICS
(For Circuit Diagram See Figure 12 In Application)
100
0.1
0.2
0.5
1.0
2.0
5.0
10
20
50
1.0 k 10 k 100 k 1.0 M
0.0001 0.001 0.01 0.1
R
TC
, RESISTANCE (W)
C, CAPACITANCE (mF)
f, OSCILLATOR FREQUENCY (kHz)
f AS A FUNCTION
OF C
(R
TC
= 56 kW)
(R
S
= 120 k)
f AS A FUNCTION
OF R
TC
(C = 1000 pF)
(R
S
2R
TC
)
V
DD
= 10 V
Figure 4. Typical C
X
versus Pulse Width
@ V
DD
= 5.0 V
Figure 5. Typical C
X
versus Pulse Width
@ V
DD
= 10 V
100
0.1
1.0
10
1000100101.0
C
X
, EXTERNAL CAPACITANCE (pF)
, PULSE WIDTH (t
W
μs)
R
X
= 100 kW
50 kW
10 kW
5 kW
T
A
= 25°C
V
DD
= 5 V
FORMULA FOR CALCULATING t
W
IN
MICROSECONDS IS AS FOLLOWS:
t
W
= 0.00247 R
X
(C
X
)
0.85
WHERE R IS IN kW, C
X
IN pF.
1000100101.0
C
X
, EXTERNAL CAPACITANCE (pF)
100
0.1
1.0
10
, PULSE WIDTH (t
W
μs)
FORMULA FOR CALCULATING t
W
IN
MICROSECONDS IS AS FOLLOWS:
t
W
= 0.00247 R
X
(C
X
)
0.85
WHERE R IS IN kW, C
X
IN pF.
R
X
= 100 kW
50 kW
10 kW
5 kW
T
A
= 25°C
V
DD
= 10 V
Figure 6. Typical C
X
versus Pulse Width
@ V
DD
= 15 V
1000100101.0
C
X
, EXTERNAL CAPACITANCE (pF)
100
0.1
1.0
10
, PULSE WIDTH (t
W
μs)
FORMULA FOR CALCULATING t
W
IN
MICROSECONDS IS AS FOLLOWS:
t
W
= 0.00247 R
X
(C
X
)
0.85
WHERE R IS IN kW, C
X
IN pF.
R
X
= 100 kW
50 kW
10 kW
5 kW
T
A
= 25°C
V
DD
= 15 V
MONOSTABLE CHARACTERISTICS
(For Circuit Diagram See Figure 11 In Application)
MC14536B
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Figure 7. Power Dissipation Test
Circuit and Waveform
Figure 8. Switching Time Test Circuit and Waveforms
V
DD
0.01 mF
CERAMIC
500 mF
I
D
C
L
C
L
C
L
V
SS
PULSE
GENERATOR
SET
RESET
8-BYPASS
IN
1
C INH
MONO-IN
OSC INH
C
B
A
D
OUT 1
OUT
2
DECODE
OUT
20 ns
20 ns
90%
10%
50%
50%
DUTY CYCLE
PULSE
GENERATOR
SET
RESET
8-BYPASS
IN
1
C INH
MONO-IN
OSC INH
C
B
A
D
OUT 1
OUT
2
DECODE
OUT
C
L
V
SS
V
DD
20 ns
20 ns
50%
IN
1
t
WL
t
WH
50%
t
PHL
90%
10%
t
PLH
t
TLH
t
THL
OUT
FUNCTIONAL TEST SEQUENCE
Test function (Figure 9) has been included for the
reduction of test time required to exercise all 24 counter
stages. This test function divides the counter into three
8−stage sections and 255 counts are loaded in each of the
8−stage sections in parallel. All flip−flops are now at a “1”.
The counter is now returned to the normal 24−stages in
series configuration. One more pulse is entered into In
1
which will cause the counter to ripple from an all “1” state
to an all “0” state.
Figure 9. Functional
Test Circuit
V
DD
V
SS
PULSE
GENERATOR
SET
RESET
8-BYPASS
IN
1
C INH
MONO-IN
OSC INH
C
B
A
D
OUT 1
OUT
2
DECODE
OUT
FUNCTIONAL TEST SEQUENCE
Inputs Outputs Comments
In
1
Set Reset 8−Bypass
Decade Out
Q1 thru Q24
All 24 stages are in Reset mode.
1 0 1 1 0
1 1 1 1 0 Counter is in three 8 stage sections in parallel mode.
0 1 1 1 0 First “1” to “0” transition of clock.
1
0
1 1 1 255 “1” to “0” transitions are clocked in the counter.
0 1 1 1 1 The 255 “1” to “0” transition.
0 0 0 0 1 Counter converted back to 24 stages in series mode.
Set and Reset must be connected together and simultaneously
go from “1” to “0”.
1 0 0 0 1 In
1
Switches to a “1”.
0 0 0 0 0 Counter Ripples from an all “1” state to an all “0” state.
MC14536B
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NOTE: When power is first applied to the device, DECODE OUT can be either at a high or low state. On the rising edge of a SET pulse
the output goes high if initially at a low state. The output remains high if initially at a high state. Because CLOCK INH is held
high, the clock source on the input pin has no effect on the output. Once CLOCK INH is taken low, the output goes low on the
first negative clock transition. The output returns high depending on the 8−BYPASS, A, B, C, and D inputs, and the clock input
period. A 2
n
frequency division (where n = the number of stages selected from the truth table) is obtainable at DECODE OUT.
A 2
0
–divided output of IN
1
can be obtained at OUT
1
and OUT
2
.
Figure 10. Time Interval Configuration Using an External Clock, Set, and Clock Inhibit Functions
(Divide−by−2 Configured)
PULSE
GEN.
PULSE
GEN.
CLOCK
8-BYPASS
A
B
C
D
RESET
OSC INH
MONO-IN
SET
CLOCK INH
IN
1
V
SS
DECODE OUT
OUT 2
OUT 1
8
16
+V
6
9
10
11
12
2
14
15
1
7
313
5
4
DECODE OUT
CLOCK INH
SET
IN
1
POWERUP
V
DD

NLV14536BDWR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Monostable Multivibrator PROGRAMMABLE TIMER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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