MX7824KCWG+ Datasheet MX7828KP+, MX7828KN+, MX7824KCWG+ | P7-P9

does not require microprocessor WAIT states. A READ

operation simultaneously initiates a conversion and

reads the previous conversion result.

Interface Mode 0

Figure 5 shows the timing diagram for Mode 0 opera-

tion. This is used with microprocessors that have WAIT

state capability, whereby a READ instruction is extend-

ed to accommodate slow-memory devices. Taking CS

and RD low latches the analog multiplexer address and

starts a conversion. Data outputs DB0–DB7 remain in

the high-impedance condition until the conversion is

complete.

There are two status outputs: Interrupt (INT

) and Ready

(RDY). RDY, an open-drain output (no internal pull-up

device), is connected to the processor’s READY/WAIT

input. RDY goes low on the falling edge of CS and goes

high impedance at the end of the conversion, when the

conversion result appears on the data outputs. If the RDY

output is not required, its external pull-up resistor can be

omitted. INT goes low when the conversion is complete

and returns high on the rising edge of CSor RD.

Interface Mode 1

Mode 1 is designed for applications where the micro-

processor is not forced into a WAIT state. Taking CS

and RD low latches the multiplexer address and starts

a conversion (Figure 6). Data from the previous conver-

sion is immediately read from the outputs (DB0–DB7).

INT goes high at the rising edge of CS or RD and goes

low at the end of the conversion. A second READ oper-

ation is required to read the result of this conversion.

The second READ latches a new multiplexer address

and starts another conversion. A delay of 2.5µs must

be allowed between READ operations. RDY goes low

on the falling edge of CS and goes high impedance at

the rising edge of CS. If RDY is not needed, its external

pull-up resistor can be omitted.

MX7824/MX7828

CMOS, High-Speed, 8-Bit ADCs

with Multiplexer

_______________________________________________________________________________________ 7

500ns

IS TRACKED

BY INTERNAL 

COMPARATORS

IS SAMPLED

AND THE FOUR MSBs

ARE LATCHED

SETUP TIME REQUIRED

BY THE INTERNAL

COMPARATORS PRIOR TO

STARTING CONVERSION

600ns

INT GOING LOW 

INDICATES THAT 

CONVERSION IS

COMPLETE AND 

THAT DATA CAN 

BE READ

1000ns

Figure 4. Operating Sequence

DATA

DATA

VALID

ADDR

VALID

ADDR

VALID

INT

RDY

ANALOG

CHANNEL

ADDRESS

RDY

CRD

HIGH IMPEDANCE

CSS

INTH

ACC2

CSH

Figure 5. Mode 0 Timing Diagram

MX7824/MX7828

_____________Analog Considerations

Reference and Input

The V

REF

+ and V

- inputs of the converter define the

zero and the full-scale of the ADC. In other words, the

voltage at V

REF

- is equal to the input voltage that pro-

duces an output code of all zeros, and the voltage at

REF

+ is equal to input voltage that produces an output

code of all ones (Figure 7).

Figure 8 shows some possible reference configura-

tions. For the MAX154/MAX158, a 0.01µF bypass

capacitor to GND should be used to reduce the high-

frequency output impedance of the internal reference.

Larger capacitors should not be used, as this degrades

the stability of the reference buffer. The 2.5V reference

output is with respect to the GND pin.

Bypassing

A 47µF electrolytic and 0.1µF ceramic capacitor should

be used to bypass the V

pin to GND. These capaci-

tors must have minimum lead length, since excess lead

length may contribute to conversion errors and instability.

If the reference inputs are driven by long lines, they

should be bypassed to GND with 0.1µF capacitors at

the reference input pins.

CMOS, High-Speed, 8-Bit ADCs

with Multiplexer

8 _______________________________________________________________________________________

DATA

NEW

DATA

ADDR

VALID

INT

RDY

ANALOG

CHANNEL

ADDRESS

RDY

ACCI

CRD

CSS

RDY

INTH

CSS

CSH

ADDR

VALID

OLD

DATA

CSH

ACCI

Figure 6. Mode 1 Timing Diagram

11111111

11111110

11111101

00000011

00000010

00000001

00000000

REF

FS–1LSB

OUTPUT

CODE

FULL-SCALE

TRANSITION

1LSB = F8 = V

REF

+ - V

REF

-

256 256



AIN INPUT VOLTAGE 

(IN TERMS OF LSBs)

Figure 7. Transfer Function

Input Current

The converters’ analog inputs behave somewhat differ-

ently from conventional ADCs. The sampled data com-

parators take varying amounts of current from the input,

depending on the cycle they are in. The equivalent cir-

cuit of the converter is shown in Figure 9a. When the

conversion starts, AIN(n) is connected to the MS and

LS comparators. Thus, AIN(n) is connected to thirty-one

1pF capacitors.

To acquire the input signal in approximately 1µs, the

input capacitors must charge to the input voltage

through the on-resistance of the multiplexer (about

600Ω) and the comparator’s analog switches (2kΩ to

5kΩ per comparator). In addition, about 12pF of stray

capacitance must be charged. The input can be mod-

eled as an equivalent RC network shown in Figure 9b.

As R

(source impedance) increases, the capacitors

take longer to charge.

Since the length of the input acquisition time is internal-

ly set, large source resistances (greater than 100Ω) will

cause settling errors. The output impedance of an op-

amp is its open-loop output impedance divided by the

loop gain at the frequency of interest. It is important

that the amplifier driving the converter input have suffi-

cient loop gain at approximately 1MHz to maintain low

output impedance.

Input Filtering

The transients in the analog input caused by the sam-

pled data comparators do not degrade the converter’s

performance, since the ADC does not “look” at the

input when these transients occur. The comparator’s

outputs track the input during the first 1µs of the con-

version, and are then latched. Therefore, at least 1µs

will be provided to charge the ADC’s input capaci-

tance. It is not necessary to filter these transients with

an external capacitor on the AIN terminals.

Sinusoidal Inputs

The MAX154/MAX158 and MX7824/MX7828 can mea-

sure input signals with slew rates as high as 157mV/µs

to the rated specifications. This means that the analog

input frequency can be as high as 10kHz without the

aid of an external track/hold. The maximum sampling

rate is limited by the conversion time (typical t

CRD

2µs) plus the time required between conversions (t

500ns). It is calculated as:

MAX

400kHz

CRD

+ t

(2.0 + 0.5) µs

MX7824/MX7828

CMOS, High-Speed, 8-Bit ADCs

with Multiplexer

_______________________________________________________________________________________ 9

MAX154

MAX158

GND

REF OUT

REF

AIN

(+)

AIN

(-)

+5V

0.1µF47µF

0.01µF

REF

MX7824

MX7828

MX584

GND

REF

AIN

(+)

AIN

(-)

+5V

2.5V

0.1µF

47µF

REF

MAX154

MAX158

MX7824

MX7828

GND

REF

AIN

(+)

AIN

(-)

+5V

0.1µF

47µF

REF

MAX154

MAX158

MX7824

MX7828

GND

* Current path must

still exist from

IN(-)

to Ground

REF

AIN

(+)

AIN

(-)

+5V

2.5V

0.1µF47µF

REF

Figure 8a. Internal Reference (MAX154/MAX158 only)

Figure 8b. External Reference +2.5V Full-Scale

Figure 8c. Power Supply as Reference

Figure 8d. Inputs Not Referenced to GND

P1-P3 P4-P6 P7-P9 P10-P12

MX7824KCWG+

Mfr. #:

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Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC 8-Bit 4Ch Precision ADC

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