RT8267
10
DS8267-02 March 2011www.richtek.com
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to ΔI
LOAD
(ESR) and also begins to charge or
discharge C
OUT
generating a feedback error signal for the
regulator to return V
OUT
to its steady-state value. During
this recovery time, V
OUT
can be monitored for overshoot or
ringing that would indicate a stability problem.
Thermal Considerations
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula :
P
D(MAX)
= ( T
J(MAX)
− T
A
) / θ
JA
Where T
J(MAX)
is the maximum operation junction
temperature, T
A
is the ambient temperature and the θ
JA
is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT8267, the maximum junction temperature is 125°C. The
junction to ambient thermal resistance θ
JA
for SOP-8
package is 120°C/W on the standard JEDEC 51-7 four-
layers thermal test board. The maximum power dissipation
at T
A
= 25°C can be calculated by following formula :
P
D(MAX)
= (125°C − 25°C) / (120°C/W) = 1.163W for
SOP-8 packages
The maximum power dissipation depends on operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance θ
JA
. For RT8267 packages, the Figure 3 of
derating curves allows the designer to see the effect of
rising ambient temperature on the maximum power
allowed.
Layout Consideration
Follow the PCB layout guidelines for optimal performance
of the RT8267.
` Keep the traces of the main current paths as short and
wide as possible.
` Put the input capacitor as close as possible to the device
pins (VIN and GND).
` LX node is with high frequency voltage swing and should
be kept at small area. Keep sensitive components away
from the LX node to prevent stray capacitive noise pick-
up.
` Place the feedback components to the FB pin as close
as possible.
` The GND and Exposed Pad should be connected to a
strong ground plane for heat sinking and noise protection.
Figure 3. Derating Curves for RT8267 Packages
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0255075100125
Ambient Temperature (°C)
Power Dissipation (W)
Four Layer PCB
SOP-8
