LTC1261CS8#TRPBF Datasheet LTC1261CS8#TRPBF, LTC1261CS8-4.5#TRPBF, LTC1261CS8-4#TRPBF | P7-P9

LTC1261

1261fb

For more information www.linear.com/LTC1261

APPLICATIONS INFORMATION

Figure 2. Block Diagram

–

CLK

550kHz

S1 S5

OUT

LTC1261 • F02

60mV

1.18V

REF

= 1.24V

ADJ

R1*

R0*

*LTC1261CS14 ONLY

OUT

–

S4 S6

–

50k

100k

226k

INTERNALLY

CONNECTED FOR

FIXED OUTPUT

VOLTAGE PARTS

124k

COMP 1

COMP 2

ADJ/COMP

REG

The output voltage is monitored by COMP1 which compares

a divided replica of the output at ADJ (COMP for fixed

output parts) to the internal reference. At the beginning

of a cycle the clock is low, forcing the output of the AND

gate low and charging the flying capacitors. The next rising

clock edge sets the RS latch, setting the charge pump to

transfer charge from the flying

capacitors to the output

capacitor. As long as the output is below the set point,

COMP1 stays low, the latch stays set and the charge pump

runs at the full 50% duty cycle of the clock gated through

the AND gate. As the output approaches the set voltage,

COMP1 will trip whenever the divided signal exceeds the

internal 1.24V reference relative to OUT. This resets the

RS latch

and truncates the clock pulses, reducing the

amount of charge transferred to the output capacitor and

regulating the output voltage. If the output exceeds the

set point, COMP1 stays high, inhibiting the RS latch and

disabling the charge pump.

COMP2 also monitors the divided signal at ADJ but it is

connected to a 1.18V reference, 5% below the main refer-

ence voltage. When the divided output exceeds this

lower

reference voltage indicating that the output is within 5%

of the set value, COMP2 goes high turning on the REG

output transistor. This is an open drain N-channel device

capable of sinking 5mA with a 3.3V V

and 8mA with

a 5V V

. When in the “off” state (divided output more

than 5% below V

REF

) the drain can be pulled above V

without damage up

to a maximum of 12V above ground.

Note that the REG output only indicates if the magnitude of

the output is below the magnitude of the set point by 5%

(i.e., V

OUT

> –4.75V for a –5V set point). If the magnitude

of the output is forced higher than the magnitude of the

set point ( i.e., to – 6V when the output is set for –5V

) the

REG output will stay low.

LTC1261

1261fb

For more information www.linear.com/LTC1261

APPLICATIONS INFORMATION

OUTPUT RIPPLE

Output ripple in the LTC1261 comes from two sources;

voltage droop at the output capacitor between clocks and

frequency response of the regulation loop. Voltage droop

is easy to calculate. With a typical clock frequency of

550kHz, the charge on the output capacitor is refreshed

once every 1.8µs. With a 15mA load and a 3.3µF output

capacitor, the output will droop by:

LOAD

•

∆t

OUT













= 15mA •

1.8µs

3.3µF













= 8.2mV

This can be a significant ripple component when the output

is heavily loaded, especially if the output capacitor is small.

If absolute minimum output ripple is required, a 10µF or

greater output capacitor should be used.

Regulation loop frequency response is the other major

contributor to output ripple. The LTC1261 regulates the

output voltage by limiting the amount of charge transferred

to the output capacitor on a

cycle-by-cycle basis. The

output voltage is sensed at the ADJ pin (COMP for fixed

output versions) through an internal or external resistor

divider from the OUT pin to ground. As the flying capaci-

tors are first connected to the output, the output voltage

begins to change quite rapidly. As soon as it exceeds the

set point COMP1 trips, switching the state of the charge

pump

and stopping the charge transfer. Because the RC

time constant of the capacitors and the switches is quite

short, the ADJ pin must have a wide AC bandwidth to be

able to respond to the output in time. External parasitic

capacitance at the ADJ pin can reduce the bandwidth to

the point where the comparator cannot respond by the

time the clock pulse finishes. When this happens

the

comparator will allow a few complete pulses through, then

overcorrect and disable the charge pump until the output

drops below the set point. Under these conditions the

output will remain in regulation but the output ripple will

increase as the comparator “hunts” for the correct value.

To prevent this from happening, an external capacitor

can be connected from ADJ (or COMP for fixed output

parts) to

ground to compensate for external parasitics and

increase the regulation loop bandwidth (Figure 3). This

sounds coutnterintuitive until we remember that the internal

reference is generated with respect to OUT, not ground.

COMP 1

1.24V

OUT

ADJ/COMP

RESISTORS ARE

INTERNAL FOR

FIXED OUTPUT PARTS

LTC1261 • F03

100pF

TO CHARGE

PUMP

REF

–

Figure 3. Regulator Loop Compensation

The feedback loop actually sees ground as its “output,” thus

the compensation capacitor should be connected across

the “top” of the resistor divider, from ADJ (or COMP) to

ground. By the same token, avoid adding capacitance

between ADJ (or COMP) and V

OUT

. This will slow down

the feedback loop and increase output ripple. A 100pF

capacitor from ADJ or COMP to ground will

compensate

the loop properly under most conditions.

OUTPUT FILTERING

If extremely low output ripple (<5mV) is required, addi-

tional output filtering is required. Because the LTC1261

uses a high 550kHz switching frequency, fairly low value

RC or LC networks can be used at the output to effectively

filter the output ripple. A 10Ω series output resistor and

a 3.3µF capacitor will cut output ripple to below 3mV

(Figure4). Further reductions can be obtained with larger

filter capacitors or by using an LC output filter.

LTC1261

1261fb

For more information www.linear.com/LTC1261

APPLICATIONS INFORMATION

Figure 4. Output Filter Cuts Ripple Below 3mV

LTC1261CS8-4

–

OUT

0.1µF

100pF

3.3µF

10Ω

COMP

LTC1261 • F04

GND

OUT

= –4V

1µF

3.3µF

CAPACITOR SELECTION

Capacitor Sizing

The performance of the LTC1261 can be affected by the

capacitors it is connected to. The LTC1261 requires bypass

capacitors to ground for both the V

and OUT pins. The

input capacitor provides most of LTC1261’s supply current

while it is charging the flying capacitors. This capacitor

should be mounted as close to the package as possible

and its value should

be at least five times larger than the

flying capacitor. Ceramic capacitors generally provide

adequate performance but avoid using a tantalum capaci-

tor as the input bypass unless there is at

least a 0.1µF

ceramic capacitor in parallel with it. The charge pump

capacitors are somewhat less critical since their peak

currents are limited by the switches inside the LTC1261.

Most applications should use 0.1µF as the

flying capaci-

tor value. Conveniently, ceramic capacitors are the most

common type of 0.1µF capacitor and they work well here.

Usually the easiest solution is to use the same capacitor

type for both the input bypass and the flying capacitors.

In applications where the maximum load current is well-

defined and output ripple is critical or input peak currents

need to be minimized, the flying capacitor values

can be

tailored to the application. Reducing the value of the flying

capacitors reduces the amount of charge transferred with

each clock cycle. This limits maximum output current, but

also cuts the size of the voltage step at the output with

each clock cycle. The smaller capacitors draw smaller

pulses of current out of V

as well, limiting peak cur-

rents and reducing the demands on

the input supply.

Table 1 shows recommended values of flying capacitor

vs maximum load capacity.

Table 1. Typical Max Load (mA) vs Flying Capacitor Value at

= 25°C, V

OUT

= –4V

FLYING

CAPACITOR

VALUE (µF)

MAX LOAD (mA)

= 5V DOUBLER MODE

MAX LOAD (mA)

= 3.3V TRIPLER MODE

0.1 22 20

0.047 16 15

0.033 8 11

0.022 4 5

0.01 1 3

The output capacitor performs two functions: it provides

output current to the load during half of the charge pump

cycle and its value helps

to set the output ripple voltage.

For applications that are insensitive to output ripple, the

output bypass capacitor can be as small as 1µF. To achieve

specified output ripple with 0.1µF flying capacitors, the

output capacitor should be at least 3.3µF. Larger output

capacitors will reduce output ripple further at the expense

of turn-on time.

Capacitor ESR

Output capacitor Equivalent Series Resistance (ESR) is

another factor to

consider. Excessive ESR in the output

capacitor can fool the regulation loop into keeping the

output artificially low by prematurely terminating the

charging cycle. As the charge pump switches to recharge

the output a brief surge of current flows from the flying

capacitors to the output capacitor. This current surge can

be as high as 100mA under full load conditions. A typical

3.3µF tantalum capacitor has 1Ω

or 2Ω of ESR; 100mA

• 2Ω = 200mV. If the output is within 200mV of the set

point this additional 200mV surge will trip the feedback

comparator and terminate the charging cycle. The pulse

dissipates quickly and the comparator returns to the

correct state, but the RS latch will not allow the charge

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

LTC1261CS8#TRPBF

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Description:

Switching Voltage Regulators Adj Sw Cap Reg Volt Inverter

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LTC1261CS8#TRPBF

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