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74ACT175MTC

P1-P3P4-P6P7-P9P10-P12
tm
74AC175, 74ACT175 Quad D-Type Flip-Flop
April 2007
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC175, 74ACT175 Rev. 1.4
74AC175, 74ACT175
Quad D-Type Flip-Flop
Features
■
I
CC
reduced by 50%
■
Edge-triggered D-type inputs
■
Buffered positive edge-triggered clock
■
Asynchronous common reset
■
True and complement output
■
Outputs source/sink 24mA
■
ACT175 has TTL-compatible inputs
General Description
The AC/ACT175 is a high-speed quad D-type flip-flop.
The device is useful for general flip-flop requirements
where clock and clear inputs are common. The informa-
tion on the D-type inputs is stored during the LOW-to-
HIGH clock transition. Both true and complemented out-
puts of each flip-flop are provided. A Master Reset input
resets all flip-flops, independent of the Clock or D-type
inputs, when LOW.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram Pin Descriptions
Order
Number
Package
Number Package Description
74AC175SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Body
74AC175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC175PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT175SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Body
74ACT175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
D
0
–D
3
Data Inputs
CP Clock Pulse Input
MR
Master Reset Input
Q
0
–Q
3
Tr ue Outputs
Q
0
–Q
3
Complement Outputs
FACT™ is a trademark of Fairchild Semiconductor Corporation.
74AC175, 74ACT175 Quad D-Type Flip-Flop
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC175, 74ACT175 Rev. 1.4 2
Logic Symbol
IEEE/IEC
Functional Description
The AC/ACT175 consists of four edge-triggered D-type
flip-flops with individual D inputs and Q and Q
outputs.
The Clock and Master Reset are common. The four flip-
flops will store the state of their individual D inputs on the
LOW-to-HIGH clock (CP) transition, causing individual Q
and Q
outputs to follow. A LOW input on the Master
Reset (MR
) will force all Q outputs LOW and Q outputs
HIGH independent of Clock or Data inputs. The AC/
ACT175 is useful for general logic applications where a
common Master Reset and Clock are acceptable.
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
t
n
=
Bit Time before Clock Pulse
t
n+1
=
Bit Time after Clock Pulse
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
Figure 1.
Inputs @ t
n
, MR
=
H Outputs @ t
n+1
D
n
Q
n
Q
n
LLH
HHL
74AC175, 74ACT175 Quad D-Type Flip-Flop
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC175, 74ACT175 Rev. 1.4 3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol Parameter Rating
V
CC
Supply Voltage –0.5V to +7.0V
I
IK
DC Input Diode Current
V
I
=
–0.5V
V
I
=
V
CC
+ 0.5V
–20mA
+20mA
V
I
DC Input Voltage –0.5V to V
CC
+ 0.5V
I
OK
DC Output Diode Current
V
O
=
–0.5V
V
O
=
V
CC
+ 0.5V
–20mA
+20mA
V
O
DC Output Voltage –0.5V to V
CC
+ 0.5V
I
O
DC Output Source or Sink Current ±50mA
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin ±50mA
T
STG
Storage Temperature –65°C to +150°C
T
J
Junction Temperature 140°C
Symbol Parameter Rating
V
CC
Supply Voltage
AC
ACT
2.0V to 6.0V
4.5V to 5.5V
V
I
Input Voltage 0V to V
CC
V
O
Output Voltage 0V to V
CC
T
A
Operating Temperature –40°C to +85°C
∆
V
/
∆
t Minimum Input Edge Rate, AC Devices:
V
IN
from 30% to 70% of V
CC
,
V
CC
@ 3.3V, 4.5V, 5.5V
125mV/ns
∆
V
/
∆
t Minimum Input Edge Rate, ACT Devices:
V
IN
from 0.8V to 2.0V, V
CC
@ 4.5V, 5.5V
125mV/ns
P1-P3P4-P6P7-P9P10-P12

74ACT175MTC

Mfr. #:
Buy 74ACT175MTC
Manufacturer:
ON Semiconductor / Fairchild
Description:
Flip Flops Qd D-Type Flip-Flop
Lifecycle:
New from this manufacturer.
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