IDT
™
/ ICS
™
LVDS/LVCMOS CLOCK GENERATOR 10 ICS8402010AKI REV. A AUGUST 28, 2008
ICS8402010I
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
unused outputs.
LVDS DRIVER TERMINATION
A general LVDS interface is shown in
Figure 4.
In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
100 Ohm Differiential Transmission Line
R1
100
3.3V
+
-
LVDS_Driver
3.3V
FIGURE 5. P.C.ASSEMBLY FOR EXPOSED PAD T HERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
VFQFN EPAD THERMAL RELEASE PAT H
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in
Figure 5.
The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”)
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to the Application
Note on the
Surface Mount Assembly
of Amkor’s Thermally/
Electrically Enhance Leadfame Base Package, Amkor Technology.
THERMAL VIA
LAND PATTERN
SOLDER
PIN
SOLDER
PIN PADPIN PAD
PIN
GROUND PLANE
EXPOSED HEAT SLUG
(GROUND PAD)
