NOT RECOMMENDED FOR
NEW DESIGNS
©2009 Integrated Device Technology, Inc.
JUNE 2009
DSC 7144/3
1
Functional Block Diagram
◆
Counter enable and repeat features
◆
Interrupt and Collision Detection Flags
◆
Separate byte controls for multiplexed bus and bus
matching compatibility
◆
Dual Cycle Deselect (DCD) for Pipelined Output Mode
◆
1.8V (±100mV) power supply for core
◆
LVTTL compatible,1.8V to 3.3V power supply for I/Os and
control signals on each port
◆
Industrial temperature range (-40°C to +85°C) is
available at 166MHz
◆
Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine
pitch Ball Grid Array (fpBGA)
◆
Supports JTAG features compliant with IEEE 1149.1
◆◆
◆◆
◆
Green parts available, see ordering information
HIGH-SPEED 1.8V
256/128K x 36
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V/2.5V/1.8V INTERFACE
IDT70P3519/99
REPEAT
R
A
0R
CNTEN
R
ADS
R
Dout0-8_R
Dout9-17_R
I/O
0R
- I/O
35R
Din_R
ADDR_R
OE
R
3R
BE
2R
BE
1R
BE
0R
R/W
R
CE
0R
CE
1R
1
0
1/0
FT/PIPE
R
1a 0a1b 0b1c 0c1d 0d
dcba
CLK
R
,
Counter/
Address
Reg.
dcba
0/1
0d 1d0c 1c
0b 1b0a 1a
B
W
2
R
B
W
1
R
B
W
0
R
FT/PIPE
R
Counter/
Address
Reg.
CNTEN
L
ADS
L
REPEAT
L
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout18-26_R
Dout27-35_R
B
W
0
L
B
W
1
L
B
W
2
L
B
W
3
L
I/O
0L
- I/O
35L
A
17L
(1)
A
0L
Din_L
ADDR_L
OE
L
7144 drw 01
BE
3L
BE
2L
BE
1L
BE
0L
R/W
L
CE
0L
CE
1L
256/128K x 36
MEMORY
ARRAY
CLK
L
abcd
FT/PIPE
L
0/1
1d 0d 1c 0c
1b 0b 1a 0a
B
W
3
R
,
JTAG
TCK
TRST
TMS
TDO
TDI
1
0
1/0
0d 1d0c 1c0b 1b0a 1a
abcd
FT/PIPE
L
1/0
1/0
INTERRUPT
COLLISION
DETECTION
LOGIC
R/
W
L
CE
0
L
CE1
L
R/
W
R
CE
0
R
CE1
R
INT
L
COL
L
INT
R
COL
R
ZZ
CONTROL
LOGIC
ZZ
L
(2)
ZZ
R
(2)
A
17R
(1)
Features:
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
◆
Low Power
◆
High-speed data access
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)
– Industrial: 3.6ns (166MHz)
◆
Selectable Pipelined or Flow-Through output mode
◆
Dual chip enables allow for depth expansion without
additional logic
◆
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
1. Address A
17
is a NC for the IDT70P3599.
+. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and the
sleep mode pins themselves (ZZx) are not affected during sleep mode.
NOTES:
