NOT RECOMMENDED FOR
NEW DESIGNS
6.42
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
23
Functional Description
The IDT70P3519/99 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse width is independent of the cycle time.
An asynchronous output enable is provided to ease asyn-
chronous bus interfacing. Counter enable inputs are also provided to stall
the operation of the address counters for fast interleaved
memory applications.
A HIGH on CE
0 or a LOW on CE1 for one clock cycle will power down
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70P3519/99 for depth
expansion configurations. Two cycles are required with CE
0 LOW and
CE
1 HIGH to re-activate the outputs.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INT
L) is asserted when the right port writes to memory location 3FFFE
(1FFFE for IDT70P3599), where a write is defined as CE
R = R/WR =
V
IL per the Truth Table. The left port clears the interrupt through access
of address location 3FFFE (1FFFE for IDT70P3599) when CEL = V
IL
and R/WL = VIH. Likewise, the right port interrupt flag (INTR) is asserted
when the left port writes to memory location 3FFFF (1FFF for IDT70P3599)
and to clear the interrupt flag (INTR), the right port must read the memory
location 3FFFF (1FFFF for IDT70P3599). The message (36 bits) at
3FFFE or 3FFFF (1FFFF or 1FFFE for IDT70P3599) is user-defined
since it is an addressable SRAM location. If the interrupt function is not used,
address locations 3FFFE and 3FFFF (1FFFF or 1FFFE for IDT70P3599)
are not used as mail boxes, but as part of the random access memory. Refer
to Truth Table III for the interrupt operation.
Collision Detetion
Collision is defined as accessing the same memory address from both
ports resulting in the potential for either reading or writing incorrect data
to a specific address. For the specific cases: (a) Both ports reading - no
data is corrupted, lost, or incorrectly output, so no collision flag is output on
either port. (b) One port writing, the other port reading - the end result of
the write will still be valid. However, the reading port might capture data
that is in a state of transition and hence the reading port’s collision flag is
output. (c) Both ports writing - there is a risk that the two ports will interfere
with each other, and the data stored in memory will not be a valid write from
either port (it may essentially be a random combination of the two).
Therefore, the collision flag is output on
both ports. Please refer to Truth
Table IV for all of the above cases.
The alert flag (COLx) is asserted on the 2nd or 3rd rising clock edge
of the affected port following the collision, and remains low for one cycle.
Please refer to Collision Detection Timing table on Page 21. During that
next cycle, the internal arbitration is engaged in resetting the alert flag (this
avoids a specific requirement on the part of the user to reset the alert flag).
If two collisions occur on subsequent clock cycles, the second collision may
not generate the appropriate alert flag. A third collision will generate the
proper alert flag. In the event that a user initiates a burst access on both
ports with the same starting address on both ports and one or both ports
writing during each access (i.e., imposes a long string of collisions on
contiguous clock cycles), the alert flag will be asserted and cleared every
other cycle. Please refer to the Collision Detection timing waveform on
Page 21.
Collision detection on the IDT70P3519/99 represents an advance in
functionality over other sync multi-ports, which have no such capability.
The IDT70P3519/99 sustains the key features of bandwidth and flexibility.
The collision detection function is very useful in the case of bursting data,
or a string of accesses made to sequential addresses, in that it indicates
a problem within the burst, giving the user the option of either repeating
the burst or continuing to watch the alert flag to see whether the number
of collisions increases above an acceptable threshold value. Offering this
function on chip also allows users to reduce their need for arbitration
circuits, typically done in CPLD’s or FPGA’s. This reduces board space
and design complexity, and gives the user more flexibility in developing
a solution.
Sleep Mode
The IDT70P3519/99 is equipped with an optional sleep or low power
mode on both ports. The sleep mode pin on both ports is asynchronous
and active high. During normal operation, the ZZ pin is pulled low. When
ZZ is pulled high, the port will enter sleep mode where it will meet lowest
possible power conditions. The sleep mode timing diagram shows the
modes of operation: Normal Operation, No Read/Write Allowed and Sleep
Mode.
For normal operation all inputs must meet setup and hold times prior
to sleep and after recovering from sleep. Clocks must also meet cycle high
and low times during these periods. Three cycles prior to asserting ZZ
(ZZx = V
IH) and three cycles after de-asserting ZZ (ZZx = VIL), the device
must be disabled via the chip enable pins. If a write or read operation occurs
during these periods, the memory array may be corrupted. Validity of data
out from the RAM cannot be guaranteed immediately after ZZ is asserted
(prior to being in sleep). When exiting sleep mode, the device must be in
Read mode (R/Wx = V
IH)when chip enable is asserted, and the chip
enable must be valid for one full cycle before a read will result in the output
of valid data.
During sleep mode the RAM automatically deselects itself. The RAM
disconnects its internal clock buffer. The external clock may continue to run
without impacting the RAMs sleep current (IZZ). All outputs will remain in
high-Z state while in sleep mode. All inputs are allowed to toggle. The RAM
will not be selected and will not perform any reads or writes.
