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DM74S74N

P1-P3P4-P5
© 2000 Fairchild Semiconductor Corporation DS006457 www.fairchildsemi.com
August 1986
Revised April 2000
DM74S74 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs
DM74S74
Dual Positive-Edge-Triggered D Flip-Flops
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered D flip-flops with complementary outputs. The infor-
mation on the D input is accepted by the flip-flops on the
positive going edge of the clock pulse. The triggering
occurs at a voltage level and is not directly related to the
transition time of the rising edge of the clock. The data on
the D input may be changed while the clock is LOW or
HIGH without affecting the outputs as long as setup and
hold times are not violated. A low logic level on the preset
or clear inputs will set or reset the outputs regardless of the
logic levels of the other inputs.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Function Table
H = HIGH Logic Level
X = Either LOW or HIGH Logic Level
L = LOW Logic Level
↑ = Positive-going Transition
* = This configuration is nonstable; that is, it will not persist when either the
preset and/or clear inputs return to its inactive (HIGH) level.
Q
0
= The output logic level of Q before the indicated input conditions were
established.
Order Number Package Number Package Description
DM74S74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74S74N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Outputs
PR CLR CLK D Q Q
LHXXH L
HL XXL H
L L X X H* H*
HH ↑ HH L
HH ↑ LL H
HH LXQ
0
Q
0
www.fairchildsemi.com 2
DM74S74
Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Note 2: C
L
= 15 pF, R
L
= 280Ω, T
A
= 25°C and V
CC
= 5V.
Note 3: C
L
= 50 pF, R
L
= 280Ω, T
A
= 25°C and V
CC
= 5V.
Note 4: The symbol (↑) indicates the rising edge at the clock pulse is used for reference.
Supply Voltage 7V
Input Voltage 5.5V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C
Symbol Parameter Min Nom Max Units
V
CC
Supply Voltage 4.75 5 5.25 V
V
IH
HIGH Level Input Voltage 2 V
V
IL
LOW Level Input Voltage 0.8 V
I
OH
HIGH Level Output Current −1mA
I
OL
LOW Level Output Current 20 mA
f
CLK
Clock Frequency (Note 2) 0 110 75 MHz
f
CLK
Clock Frequency (Note 3) 0 95 65 MHz
t
W
Pulse Width Clock HIGH 6
(Note 2) Clock LOW 7.3
ns
Clear LOW 7
Preset LOW 7
t
W
Pulse Width Clock HIGH 8
(Note 3) Clock LOW 9
ns
Clear LOW 9
Preset LOW 9
t
SU
Setup Time (Note 2)(Note 4) 3↑ ns
t
SU
Setup Time (Note 3)(Note 4) 3↑ ns
t
H
Input Hold Time (Note 2)(Note 4) 2↑ ns
t
H
Input Hold Time (Note 3)(Note 4) 2↑ ns
T
A
Free Air Operating Temperature 0 70 °C
3 www.fairchildsemi.com
DM74S74
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 5: All typicals are at V
CC
= 5V, T
A
= 25°C.
Note 6: Clear is tested with preset HIGH and preset is tested with clear HIGH.
Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 8: With all outputs OPEN, I
CC
is measured with the Q and Q outputs HIGH in turn. At the time of measurement, the clock is grounded.
Switching Characteristics
at V
CC
= 5V and T
A
= 25°C
Symbol Parameter Conditions Min
Typ
Max Units
(Note 5)
V
I
Input Clamp Voltage V
CC
= Min, I
I
= − 18 mA −1.2 V
V
OH
HIGH Level V
CC
= Min, I
OH
= Max
2.7 3.4 V
Output Voltage V
IL
= Max, V
IH
= Min
V
OL
LOW Level V
CC
= Min, I
OL
= Max
0.5 V
Output Voltage V
IH
= Min, V
IL
= Max
I
I
Input Current @ Max Input Voltage V
CC
= Max, V
I
= 5.5V 1 mA
I
IH
HIGH Level V
CC
= Max D 50
Input Current V
I
= 2.7V Clear 150
µA
Preset 100
Clock 100
I
IL
LOW Level V
CC
= Max D −2
Input Current V
I
= 0.5V Clear −6
mA
(Note 6) Preset −4
Clock −4
I
OS
Short Circuit Output Current V
CC
= Max (Note 7) −40 −100 mA
I
CC
Supply Current V
CC
= Max, (Note 8) 30 50 mA
R
L
= 280Ω
Symbol Parameter
From (Input)
C
L
= 15 pF C
L
= 50 pF Units
To (Output) Min Max Min Max
f
MAX
Maximum Clock Frequency 75 65 MHz
t
PLH
Propagation Delay Time
Preset to Q 6 9 ns
LOW-to-HIGH Level Output
t
PLH
Propagation Delay Time
Clear to Q 69ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Preset to Q 13.5 17 nsHIGH-to-LOW Level Output
(Clock HIGH)
t
PHL
Propagation Delay Time
Preset to Q
814nsHIGH-to-LOW Level Output
(Clock LOW)
t
PHL
Propagation Delay Time
Clear to Q 13.5 16 nsHIGH-to-LOW Level Output
(Clock HIGH)
t
PHL
Propagation Delay Time
Clear to Q 8 13 nsHIGH-to-LOW Level Output
(Clock LOW)
t
PLH
Propagation Delay Time
Clock to Q or Q 912ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Clock to Q or Q 914ns
HIGH-to-LOW Level Output
P1-P3P4-P5

DM74S74N

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Description:
Flip Flops Dl D-Type Flip-Flop
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