NJM78LR05DU-TE1

NJM78LR05
-
4
-
Ver.2009-05-18
APPLICATION CIRCUIT
td [ms] = 100×Cd [µF]
Note 1 : When the capacitance Cd is too large, the actual delay time is shorter than the calculated result because an
electrical charge of Cd is discharged incompletely.
Solution of above problem :
(1) Connect SBD between output terminal and Cd terminal. Please refer to the fallowing circuit.
(2) Select larger capacitance, C
IN
than Cd.
NJM78LR05
-
5
-
Ver.2009-05-18
TIMING CHART
1
When the input voltage is up to about 0.8V, some voltage is outputted at the reset output because the NJM78LR05
operation is unstable.
2
When the input voltage goes over about 0.8V, the reset output becomes “L”.
3
The output voltage is rising up with the input voltage.
4
When the output voltage goes over (V
RT
+V
RTH
), the delay circuit of reset output activates.
V
RT
: Reset Threshold Voltage
V
RTH
: Reset Threshold Hysterisis Voltage
5
After the reset output delay time td has passed, the reset output becomes “H”.
6
The output voltage is falling down with the input voltage.
7
When the output voltage is less than V
RT
, the reset output becomes “L”.
NJM78LR05
-
6
-
Ver.2009-05-18
TYPICAL CHARACTERISTICS
Reset Output Voltage vs. Output Voltage Line Regulation
Load Regulation Dropout Voltage
Quiescent Current vs. Input Voltage Output Short Current vs. Input Voltage

NJM78LR05DU-TE1

Mfr. #:
Manufacturer:
NJR (New Japan Radio)
Description:
Linear Voltage Regulators 3 T Pos Vs W/Reset
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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