TDA10025HN/C1,518

1. General description
The TDA10025HN is a Dual Cable Downstream Processor.
The Cable Downstream Processor (CDP) implements the physical interfaces and
protocols required to provide the highest quality services of an in-band DOCSIS,
EuroDOCSIS, DVB and OpenCable Set-Top Box (STB). The downstream signals are
digitized by 12-bit ADC and passed to the Demod and Forward Error Correction (FEC)
blocks, which do all the cable physical layer processing. This processing includes
demodulating and Annex A (Europe), Annex B (US) or Annex C (Japan) FEC for the
in-band data.
2. Features and benefits
QPSK, 16 QAM, 32 QAM, 64 QAM, 128 QAM and 256 QAM Demodulator
ITU-T J83 Annex A, B and C FEC
Transport Stream Multiplex Frame (TSMF) module for Annex C compliance
Time interleaved parallel mode or serial mode for Transport Stream (TS) interface
On chip PLL for crystal frequency multiplication (16 MHz external)
Reuse of the tuner clock, saving one crystal
Embedded 12-bit ADC
3.3 V and 1.2 V power supplies
Low power < 235 mW for dual stream operation
Small size package
Low cost Bill Of Material (BOM)
TDA10025HN
Dual cable demodulator
Rev. 1 — 22 August 2011 Product short data sheet
TDA10025HN_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product short data sheet Rev. 1 — 22 August 2011 2 of 8
NXP Semiconductors
TDA10025HN
Dual cable demodulator
3. Quick reference data
[1] T
amb
=25C, V
DD(1V2)
and V
DD(3V3)
typical.
[2] T
j
= 120 C, V
DD(1V2)
and V
DD(3V3)
maximum.
4. Ordering information
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
P power dissipation Standby mode:
all 3 ADC in Power-down
mode and all clocks disabled
-10
[1]
30
[2]
mW
operation mode:
1.2 V supply voltage; 2
simultaneous DVB-C
demodulations (256 QAM
6.9 Msps)
- 205
[1]
280
[2]
mW
3.3 V supply voltage; 2
simultaneous DVB-C
demodulations (256 QAM
6.9 Msps)
-30
[1]
50
[2]
mW
P
tot
total power dissipation 2 simultaneous DVB-C
demodulations (256 QAM
6.9 Msps)
- 235
[1]
330
[2]
mW
V
DD(1V2)
supply voltage (1.2 V) 1.15 1.2 1.3 V
V
DD(3V3)
supply voltage (3.3 V) 3.0 3.3 3.6 V
V
IH
HIGH-level input voltage V
DD(3V3)
related input levels 2.0 - V
DD(3V3)
+
0.5
V
V
IL
LOW-level input voltage 0.5 - +0.8 V
Table 2. Ordering information
Type number Package
Name Description Version
TDA10025HN/C1 HVQFN48 plastic thermal enhanced very thin quad flat package;
no leads; 48 terminals; body 7 7 0.85 mm
SOT619-1
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TDA10025HN_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product short data sheet Rev. 1 — 22 August 2011 3 of 8
NXP Semiconductors
TDA10025HN
Dual cable demodulator
5. Block diagram
Fig 1. Block diagram
001aal859
ADC 0
(12-BIT)
TRANSPORT
MUX
TSMF 0
TS0
TS output
TS0
CABLE
DOWNSTREAM
PROCESSOR 0
ADC input 0
ADC 1
(12-BIT)
TSMF 1
TS1 TS1
CABLE
DOWNSTREAM
PROCESSOR 1
ADC data 1
ADC data 0
ADC
data 0
ADC input 1
RGU
distributes resets
to all blocks
CGU
distributes clocks
to all blocks
CONFIG
commands settings for
different blocks
I2C-BUS
TO
DTL-MMIO
I2C-bus interface

TDA10025HN/C1,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Modulator / Demodulator Dual Cable (QAM) Demodulator
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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