ISL9108IRZ-T

10
FN6612.0
December 21, 2007
Mode Selection
The MODE pin is provided on ISL9107 and ISL9108 to
select the operation mode. When it is driven to logic low or
ground, the regulator operates in forced PWM mode. Under
forced PWM mode, the device remains at the fixed PWM
operation (typical at 1.6MHz), regardless of if the load
current is high or low.
When the MODE pin is driven to logic high or connected to
input voltage V
IN
, the regulator operates in either SKIP
mode or fixed PWM mode depending on the different load
conditions.
Overcurrent Protection
The overcurrent protection is provided when an overload
condition happens. It is realized by monitoring the CSA output
with the OCP comparator, as shown in Figure 17. When the
current at P-Channel MOSFET is sensed to reach the current
limit, the OCP comparator is triggered to turn off the
P-Channel MOSFET immediately.
Short-Circuit Protection
As shown in Figure 17, the device has a Short-Circuit
Protection (SCP) comparator, which monitors the FB pin
voltage for output short-circuit protection. When the FB
voltage is lower than 0.2V, the SCP comparator forces the
PWM oscillator frequency to drop to 1/3 of its normal
operation frequency.
Soft Start-Up
The soft start-up eliminates the inrush current during the
circuit start-up. The soft-start block outputs a ramp reference
to both the voltage loop and the current loop. The two ramps
limit the inductor current rising speed as well as the output
voltage speed so that the output voltage rises in a controlled
fashion. At the very beginning of the start-up, the output
voltage is less than 0.2V; hence the PWM operating
frequency is 1/3 of the normal frequency.
Power MOSFETs
The power MOSFETs are optimized to achieve better
efficiency. The ON-resistance for the P-Channel MOSFET is
typically 0.16Ω and the typical ON-resistance for the
N-Channel MOSFET is 0.15Ω.
Low Dropout Operation
The ISL9107 and ISL9108 feature low dropout operation to
maximize the battery life. When the input voltage drops to a
level that the device can no longer operate under switching
regulation to maintain the output voltage, the P-Channel
MOSFET is completely turned on (100% duty cycle). The
dropout voltage under such condition is the product of the
load current and the ON-resistance of the P-Channel
MOSFET. Minimum required input voltage V
IN
under this
condition is the sum of the output voltage plus the voltage
drop cross the inductor and the P-Channel MOSFET switch.
Thermal Shut Down
The ISL9107 and ISL9108 provide a built-in thermal
protection function. The thermal shutdown threshold
temperature is typical +160°C with typical +25°C hysteresis.
When the internal temperature is sensed to reach +150°C,
the regulator is completely shut down and as the
temperature is sensed to drop to +125°C (typical), the device
resumes operation starting from the soft start-up.
RSI Signal
The RSI signal is an input signal, which can reset the PG
signal. As shown in Figure 17, the power-good signal is
gated by the RSI signal. When the RSI is high, the PG signal
remains low, regardless of the output voltage condition. This
function is provided on ISL9107 only.
Power-Good
The ISL9107 offers a power-good (PG) signal. When the
output voltage is not within the power-good window, the PG
pin outputs an open-drain low signal. When the output
voltage is within the power-good window, an internal
power-good signal is issued to turn off the open-drain
MOSFET so that the PG pin can be externally pulled to high.
FIGURE 19. SKIP MODE OPERATION WAVEFORMS
8 CYCLES
CLOCK
I
L
V
OUT
0
V
OUT_NOMINAL
20% PEAK CURRENT LIMIT
1.015*V
OUT_NOMINAL
ISL9107, ISL9108
11
FN6612.0
December 21, 2007
The rising edge of the PG output is delayed by 215ms
(typical) from the time the power-good signal is issued. This
function is provided on ISL9107 only.
Applications Information
Inductor and Output Capacitor Selection
To achieve better steady state and transient response,
typically a 2.2µH inductor can be used. The peak-to-peak
inductor current ripple can be expressed as in Equation 1:
In Equation 1, usually the typical values can be used but to
have a more conservative estimation, the inductance should
consider the value with worst case tolerance; and for
switching frequency (f
S
), the minimum f
S
from the “Electrical
Specifications” table on page 2 can be used.
To select the inductor, its saturation current rating should be
at least higher than the sum of the maximum output current
and half of the delta calculated from Equation 1. Another
more conservative approach is to select the inductor with the
current rating higher than the P-Channel MOSFET peak
current limit.
Another consideration is the inductor DC resistance since it
directly affects the efficiency of the converter. Ideally, the
inductor with the lower DC resistance should be considered
to achieve higher efficiency.
Inductor specifications could be different from different
manufacturers so please check with each manufacturer if
additional information is needed.
For the output capacitor, a ceramic capacitor can be used
because of the low ESR values, which helps to minimize the
output voltage ripple. A typical value of 10µF/6.3V ceramic
capacitor should be enough for most of the applications and
the capacitor should be X5R or X7R.
Input Capacitor Selection
The main function for the input capacitor is to provide
decoupling of the parasitic inductance and to provide filtering
function to prevent the switching current from flowing back to
the battery rail. A 10µF/6.3V ceramic capacitor (X5R or X7R)
is a good starting point for the input capacitor selection.
Output Voltage Setting Resistor Selection
The voltage divider resistors (R
2
and R
3
), as shown in
Figure 16, set the desired output voltage value. The output
voltage can be calculated using Equation 2:
where V
FB
is the feedback voltage (typically it is 0.8V). The
current flowing through the voltage divider resistors can be
calculated as V
O
/(R
2
+ R
3
), so larger resistance is desirable
to minimize this current. On the other hand, the FB pin has
leakage current that will cause error in the output voltage
setting. The leakage current has a typical value of 0.1µA. To
minimize the accuracy impact on the output voltage, select
the R
3
no larger than 200kΩ.
C
3
(shown in Figure 16) is highly recommended to be added
for improving stability and achieving better transient
response. C
3
can be calculated using Equation 3:
Table 1 provides the recommended component values for
some output voltage options.
Layout Recommendation
The PCB layout is a very important converter design step to
make sure the designed converter works well, especially
under the high current, high switching frequency condition.
For ISL9107 and ISL9108, the power loop is composed of
the output inductor (L), the output capacitor (C
OUT
), the SW
pin and the GND pin. It is necessary to make the power loop
as small as possible and the connecting traces among them
should be direct, short and wide; the same type of traces
should be used to connect the VIN pin, the input capacitor
C
IN
and its ground. The switching node of the converter, the
SW pin, and the traces connected to this node are very
noisy, so keep the voltage feedback trace and other noise
sensitive traces away from these noisy traces.
The input capacitor should be placed as close as possible to
the VIN pin. The ground of the input and output capacitors
should be connected as close as possible as well.
The heat of the IC is mainly dissipated through the thermal
pad. Maximizing the copper area connected to the thermal
pad is preferable. In addition, a solid ground plane is helpful
for EMI performance.
ΔI
V
O
1
V
O
V
IN
---------
⎝⎠
⎜⎟
⎛⎞
Lf
S
-------------------------------------- -
=
(EQ. 1)
V
O
V
FB
1
R
2
R
3
-------
+
⎝⎠
⎜⎟
⎛⎞
=
(EQ. 2)
TABLE 1. ISL9107 AND ISL9108 RECOMMENDED CIRCUIT
CONFIGURATION vs V
OUT
V
OUT
(V) L H) C
2
(µF) R
2
(kΩ)C
3
(pF) R
3
(kΩ)
0.8 2.2 10 0 N/A 100
1.0 2.2 10 44.2 470 178
1.2 2.2 10 80.6 270 162
1.5 2.2 10 84.5 270 97.6
1.8 2.2 10 100 220 80.6
2.5 2.2~3.3 10~22 100 220 47.5
2.8 2.2~3.3 10~22 100 220 40.2
3.3 2.2~3.3 10~22 102 220 32.4
C
3
1
2 π× R
2
7.3kHz××
---------------------------------------------------- -
=
(EQ. 3)
ISL9107, ISL9108
12
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FN6612.0
December 21, 2007
ISL9107, ISL9108
Dual Flat No-Lead Plastic Package (DFN)
//
NX (b)
SECTION "C-C"
5
(A1)
BOTTOM VIEW
A
6
AREA
INDEX
C
C
0.10
0.08
SIDE VIEW
0.15
2X
E
A
B
C0.15
D
TOP VIEW
CB
2X
6
8
AREA
INDEX
NX L
E2
E2/2
REF.
e
N
(Nd-1)Xe
(DATUM A)
(DATUM B)
5
0.10
87
D2
BA
M
C
N-1
12
PLANE
SEATING
C
A
A3
NX b
D2/2
NX k
FOR EVEN TERMINAL/SIDE
TERMINAL TIP
C
L
e
L
CC
L8.2x3
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.80 0.90 1.00 -
A1 - - 0.05 -
A3 0.20 REF -
b 0.20 0.25 0.32 5,8
D 2.00 BSC -
D2 1.50 1.65 1.75 7,8
E 3.00 BSC -
E2 1.65 1.80 1.90 7,8
e 0.50 BSC -
k0.20 - - -
L 0.30 0.40 0.50 8
N 8 2
Nd 4 3
Rev. 0 6/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.25mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.

ISL9108IRZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Switching Voltage Regulators W/ANNEAL LW IQ BUCKG W/INT FET NO PG/RS
Lifecycle:
New from this manufacturer.
Delivery:
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