16
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723611
CMOS SyncFIFO
TM
64 x 36
64 x 36
FEBRUARY 13, 2009
Figure 8. Timing for
AFAF
AFAF
AF
when the FIFO is Almost-Full
Figure 9. Timing for Mail1 Register and
MBF1 MBF1
MBF1 MBF1
MBF1
Flag
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than t
SKEW2, then AF may transition HIGH one CLKB cycle later than shown.
2. FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = L, MBB = L).
NOTE:
1. Port-B parity generation off (PGB = L)
AF
CLKA
ENB
ENA
CLKB
1
t
SKEW2
(1)
t
ENS2
t
ENH2
t
PAF
t
ENS2
t
ENH2
t
PAF
[64-(X+1)] Words in FIFO
(64-X) Words in FIFO
3024 drw 11
2
CLKA
ENA
A0 - A35
MBA
CSA
W/RA
CLKB
MBF1
CSB
MBB
ENB
B0 - B35
W/RB
W1
t
ENS1
t
ENH1
t
DS
t
DH
t
PMF
t
PMF
t
EN
t
MDV
t
PMR
t
ENS2
t
ENH2
t
DIS
W1 (Remains valid in Mail1 Register after read)FIFO Output Register
t
ENS1
t
ENH1
t
ENS1
t
ENH1
t
ENS1
t
ENH1
3024 drw 12
