IR1168S
www.irf.com © 2009 International Rectifier
10
Lead Definitions
PIN# Symbol Description
1 GATE1 Gate Drive Output 1
2 VCC Supply Voltage
3 VS1 Sync FET 1 Source Voltage Sense
4 VD1 Sync FET 1 Drain Voltage Sense
5 VD2 Sync FET 2 Drain Voltage Sense
6 VS2 Sync FET 2 Source Voltage Sense
7 GND Analog and Power Ground
8 GATE2 Gate Drive Output 2
Lead Assignments
4
3
2
1
5
6
7
8
VD2VD1
GND
GATE2
VCC
VS1
VS2
GATE1
IR1168S
www.irf.com © 2009 International Rectifier
11
Detailed Pin Description
VCC: Power Supply
This is the supply voltage pin of the IC and it is monitored by the under voltage lockout circuit. It is possible to turn
off the IC by pulling this pin below the minimum turn off threshold voltage, without damage to the IC.
To prevent noise problems, a bypass ceramic capacitor connected to Vcc and COM should be placed as close as
possible to the IR1168. This pin is not internally clamped.
GND: Ground
This is ground potential pin of the integrated control circuit. The internal devices and gate driver are referenced to
this point.
VD1 and VD2: Drain Voltage Sense
These are the two high-voltage pins used to sense the drain voltage of the two SR power MOSFETs. Routing
between the drain of the MOSFET and the IC pin must be particularly optimized.
VS1 and VS2: Source Voltage Sense
These are the two differential sense pins for the two source pins of the two SR power MOSFETs. This pin must
not be connected directly to the GND pin (pin 7) but must be used to create a kelvin contact as close as possible
to the power MOSFET source pin.
GATE1 and GATE2: Gate Drive Outputs
These are the two gate drive outputs of the IC. The gate voltage is internally clamped and has a +1A/-4A peak
drive capability. Although this pin can be directly connected to the synchronous rectifier (SR) MOSFET gate, the
use of gate resistor is recommended (specifically when putting multiple MOSFETs in parallel). Care must be taken
in order to keep the gate loop as short and as small as possible in order to achieve optimal switching performance.
IR1168S
www.irf.com © 2009 International Rectifier
12
Application Information and Additional Details
State Diagram
POWER ON
Gate Inactive
UVLO MODE
VCC < VCCon
Gate Inactive
I
CC
= I
CC START
NORMAL
Gate Active
Gate PW MOT
VCC > VCCon
VCC < VCCuvlo
UVLO Mode:
The IC is in the UVLO mode when the VCC pin voltage is below VCCUVLO.
The UVLO mode is accessible from
any other state of operation. In the UVLO state, most of the internal circuitry is unbiased and the IC draws a
quiescent current of ICCSTART.
The IC remains in the UVLO condition until the voltage on the VCC pin exceeds the VCC turn on threshold
voltage, VCC ON.
Normal Mode:
The IC enters in normal operating mode once the UVLO voltage has been exceeded. At this point the gate
drivers
are operating and the IC will draw a maximum of ICC from the supply voltage source.

IR1168STRPBF

Mfr. #:
Manufacturer:
Infineon / IR
Description:
Gate Drivers Dual Smartrectifier Drvr IC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet