25
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO
TM
65,536 x 9 and 131,072 x 9
Figure 22. Block Diagram of 131,072 x 9 and 262,144 x 9 Depth Expansion
For a full expansion configuration, the amount of time it takes for IR of the first
FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. Note that extra cycles should be added for the possibility that the
tSKEW1 specification is not met between RCLK and transfer clock, or WCLK and
transfer clock, for the IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK,
whichever is faster. Both these actions result in data moving, as quickly as
possible, to the end of the chain and free locations to the beginning of the
chain.
Dn
INPUT READY
WRITE ENABLE
WRITE CLOCK
WEN
WCLK
IR
DATA IN
RCLK
READ CLOCK
RCLK
REN
OE
OUTPUT ENABLE
OUTPUT READY
Qn
Dn
IR
GND
WEN
WCLK
OR
REN
OE
Qn
READ ENABLE
OR
DATA OUT
IDT
72V281
72V291
TRANSFER CLOCK
4513 drw 25
n
n n
FWFT/SI FWFT/SI
FWFT/SI
IDT
72V281
72V291
