North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
1
RevA0215
CTSLV
3
9
9
LVPECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable
MLP8, MSOP8 Not recommended for new designs
DESCRIPTION
The CTSLV399 is a specialized oscillator gain stage with an LVDS output buffer including an enable. The
selectable enable input allows continuous oscillator operation by only controlling the Q
HG
/Q¯
HG
outputs.
The CTSLV399 provides adjustable internal pull-down current sources for the Q/Q¯ outputs. Internal input
biasing further reduces the number of needed external components
ENGINEERING NOTES
The CTSLV399 is a specialized oscillator gain stage with LVDS output buffer including an enable. The
enable input (EN) allows continuous oscillator operation by only controlling the Q
HG
/Q¯
HG
outputs.
The CTSLV399 also provides a V
BB
and 470 internal bias resistors from D to V
BB
and D¯ to V
BB
. The V
BB
pin can support 1.5 mA sink/source current. Bypassing V
BB
to ground with a 0.01 F capacitor is
recommended.
Functionality MLP8 Package (CTSLV399NG)
The MLP8, NG options of the CTSLV399, provide a PECL/ECL level enable input ( EN¯¯¯). When the EN¯¯¯
input is LOW, the Q¯ and Q
HG
/Q¯
HG
outputs pass data from the inputs. When EN¯¯¯ is HIGH, the Q¯ output
continues to pass data while the Q
HG
output is forced high and the Q¯
HG
output is forced low.
Only the Q¯ output operates with a current source (4 mA) to V
EE
. This is accomplished by internal bonding
of CS-SEL. An external resistor may also be used to increase pull-down current to a maximum of 25mA
(includes 4mA on-chip current source).
The CTSLV399NB and CTSLV399ND versions operate with a single ended data input (D). The D¯ input is
internally bonded directly to the V
BB
pin bypassing the 470 bias resistor.
Functionality MLP8 Package (CTSLV399N) & MSOP8 Package (CTSLV399T)
The MSOP8 (T) and MLP8 (N) versions of the CTSLV399 provide a CMOS/TTL level enable input (EN).
When the EN input is HIGH, the Q¯ and Q
HG
/Q¯
HG
outputs pass data from the inputs. When EN is LOW, the
Q¯ output continues to pass data while the Q
HG
output is forced high and the Q¯
HG
output is forced low.
Only the Q¯ output operates with a current source (4 mA) to V
EE
. This is accomplished by internal bonding
of CS-SEL. An external resistor may also be used to increase pull-down current to a maximum of 25mA
(includes 4mA on-chip current source).
The MSOP8 (T) and MLP8 (N) CTSLV399 operates with a single ended data input (D). The D¯ input is
in
te
rn
a
ll
y
bo
n
ded
d
ir
ect
l
y
to
t
h
e
V
BB
p
in
bypass
in
g
t
h
e
47
0
b
i
as
r
es
i
sto
r.
BLOCK DIAGRAM
FEATURES
Minimizes External Components
Selectable Enable Polarity and Threshold
(CMOS or PECL)
3V to 5.5V Power Supply
Similar Operation as CTS100LVEL16VT
Except with LVDS Outputs
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
2
RevA0215
CTSLV
3
9
9
LVPECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable
MLP8, MSOP8 Not recommended for new designs
Enable Truth Table
EN-SEL
EN/ EN
Q/Q¯ Q
HG
Q¯
HG
NC
PECL Low, V
EE
or NC Data Data Data
PECL High or V
CC
Data High Low
V
EE
1
CMOS/TTL Low, V
EE
or NC Data High Low
CMOS/TTL High or V
CC
2
Data Data Data
1 EN-SEL connections must be less than 1.
2
An external 20k pull-up resistor between EN and V
CC
ensures a High when the
EN pin is not driven.
Timing Diagram
Current Source Truth Table
CS-SEL Q Q¯
NC 4mA typ 4mA typ
V
EE
1
8mA typ 8mA typ
V
CC
1
0 4mA typ
1
Connection must be less than 1.
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
3
RevA0215
CTSLV
3
9
9
LVPECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable
MLP8, MSOP8 Not recommended for new designs
Application Circuit for CMOS inputs
Recommended Component Values for CMOS Single Ended Inputs
Input Type
R1
Value
AC Coupled (C2 in
circuit)
DC Coupled (C2
shorted)
3.3 V CMOS 1.1 k 2.0 k
5.0 V CMOS 1.6 k 3.3 k
R1 should be chosen so that the input swing on the D input with respect to D¯ is
in the range of ±80 to ±1000 mV, per the AC Characteristics table and the D
input is < ±750 mV with respect to V
BB
.

CTSLV399TG

Mfr. #:
Manufacturer:
CTS Electronic Components
Description:
Clock Buffer LVPECL/LVDS Osc Gain Buff w/Select Enable
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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