LT8582
19
8582f
APPLICATIONS INFORMATION
Table 4 calculates the power dissipation of one
channel of the LT8582 for a particular boost
application (V
IN
= 5V, V
OUT
= 12V, I
OUT
= 0.8A, f
OSC
= 1.5MHz,
V
D
= 0.5V, V
CESAT
= 0.270V).
From P
TOTAL
in Table 4, die junction temperature can be
calculated using the appropriate thermal resistance number
and worst-case ambient temperature:
T
J
= T
A
+ θ
JA
• P
TOTAL
where T
J
= die junction temperature, T
A
= ambient tem-
perature and θ
JA
is the thermal resistance from the silicon
junction to the ambient air.
The published θ
JA
value is 34°C/W for the 7mm × 4mm
24-pin DFN package package. In practice, lower θ
JA
values
are realizable if board layout is performed with appropriate
grounding (accounting for heat sinking properties of the
board) and other considerations listed in the Board Layout
Guidelines section. For instance, a θ
JA
value of ~16°C/W
was consistently achieved for DFN packages of the LT8582
(at V
IN
= 5V, V
OUT
= 12V, I
OUT
= 0.8A, f
OSC
= 1.5MHz) when
board layout was optimized as per the suggestions in the
Board Layout Guidelines section.
Junction Temperature Measurement
The duty cycle of CLKOUT2 is linearly proportional to die
junction temperature (T
J
) near the CLKOUT2 pin. To get an
accurate reading, measure the duty cycle of the CLKOUT
signal and use the following equation to approximate the
junction temperature:
T
J
=
DC
CLKOUT
34.5%
0.3%
where DC
CLKOUT
is the CLKOUT duty cycle in % and T
J
is
the die junction temperature in °C. Although the absolute
die temperature can deviate from the above equation by
±10°C, the relationship between the CLKOUT duty cycle and
change in die temperature is well defined. A 3% increase
in CLKOUT duty cycle corresponds to ~10°C increase in
die temperature.
Note that the CLKOUT pin is only meant to drive capacitive
loads up to 120pF.
Thermal Lockout
When the die temperature exceeds 165°C (see Operation
Section), a fault condition occurs and the part goes into
thermal lockout. The fault condition ceases when the die
temperature drops to ~160°C (nominal).
Table 4. Calculations Example with V
IN
= 5V, V
OUT
= 12V, I
OUT
= 0.8A, f
OSC
= 1.5MHz, V
D
= 0.5V, V
CESAT
= 0.27V
DEFINITION OF VARIABLES EQUATION DESIGN EXAMPLE VALUE
DC = Switch Duty Cycle
DC =
V
OUT
–V
IN
+ V
D
V
OUT
+ V
D
–V
CESAT
DC =
12V 5V + 0.5V
12V + 0.5V 0.270V
DC = 61.3%
I
IN
= Average Input Current
η = Power Conversion Efficiency
(typically 88% at high currents)
I
IN
=
V
OUT
•I
OUT
V
IN
η
I
IN
=
12V 0.8A
5V 0.88
I
IN
= 2.18A
P
SW
= Switch I
2
R Loss
R
SW
= Switch Resistance (typically
95m combined SWA and SWB)
P
SW
= DC • I
IN
2
• R
SW
P
SW
= 0.613 • (2.18A)
2
• 95m P
SW
= 277mW
P
BAC
= Base Drive Loss (AC) P
BAC
= 13ns • I
IN
• V
OUT
• f
OSC
P
BAC
= 13ns • 2.18A • 12V • 1.5MHz P
BAC
= 511mW
P
BDC
= Base Drive Loss (DC)
P
BDC
=
V
IN
•I
IN
•DC
β
SW _at_I
IN
P
BDC
=
5V 2.18A 0.613
50
P
BDC
= 134mW
P
INP
= Chip Bias Loss P
INP
= 11mA • V
IN
P
INP
= 11mA • 5V P
INP
= 55mW
P
TOTAL
= 977mW
Note: These power calculations are for one channel of the LT8582. The power consumption of both channels should be taken into account when
calculating die temperature.
LT8582
20
8582f
APPLICATIONS INFORMATION
SWITCHING FREQUENCY
There are several considerations in selecting the operat-
ing frequency of the converter. The first is staying clear
of sensitive frequency bands, which cannot tolerate any
spectral noise. For example, in RF communication prod-
ucts with a 455kHz IF, switching above 600kHz is desired.
Communication products with sensitivity to 1.1MHz would
require to set the switching frequency to 1.5MHz or higher.
Also, like any other switching regulator, harmonics of much
higher frequency than the switching frequency are also
produced. The second consideration is the physical size
of the converter. As the operating frequency goes up, the
inductor and filter capacitors go down in value and size.
The trade-off is efficiency, since the switching losses due
to inductor AC loss, NPN base drive (see Thermal Calcula-
tions), Schottky diode charge and other capacitive loss
terms increase proportionally with frequency.
Oscillator Timing Resistor (R
T
)
The operating frequency of the LT8582 can be set by the
internal free running oscillator. When the SYNC pin for a
channel is driven low (< 0.4V), the oscillator frequency
for that channel is set by a resistor from the RT pin to
ground. The oscillator frequency is calculated using the
following formula:
f
OSC
=
81.6
R
T
+ 1
where f
OSC
is in MHz and R
T
is in k. Conversely, R
T
(in k) can be calculated from the desired frequency (in
MHz) using:
R
T
=
81.6
f
OSC
–1
Clock Synchronization
The operating frequency of each channel of the LT8582
can be set by an external source by simply providing
a clock into the SYNC pin for that channel (R
T
resistor
still required). The LT8582 will revert to its internal free
running oscillator clock (set by the R
T
resistor) when the
SYNC pin is driven below 400mV for several free running
clock periods.
Driving the SYNC pin of a channel high for an extended
period of time effectively stops the oscillator for that chan-
nel. As a result, the switching operation for that channel of
the LT8582 will stop and the CLKOUT pin of that channel
will be pulled low.
The duty cycle of the SYNC signal must be between 20%
and 80% for proper operation. Also, the frequency of the
SYNC signal must meet the following two criteria:
(1) SYNC may not toggle outside the frequency range
of 200kHz to 2.5MHz.
(2) The SYNC frequency can be higher than the free run-
ning oscillator frequency (as set by the R
T
resistor),
f
OSC
, but should not be less than 25% below f
OSC
.
Clock Synchronization of Additional Regulators
The CLKOUT pins of the LT8582 can be used to synchro-
nize additional switching regulators or other channels of
LT8582s, as shown in the Typical Application figure on
the front page.
The frequency of channel 1 of the LT8582 is set by the
external R
T
resistor. The SYNC pin of channel 2 of the
LT8582 is driven by the CLKOUT pin of channel 1 of the
LT8582. Channel 1’s CLKOUT pin has a 50% duty cycle
intended for driving SYNC2 and is 180° out of phase for
reduced input ripple or multiphase topologies.
Note that the RT pin of channel 2 of the LT8582 must have
a resistor tied to ground. It takes a few clock cycles for the
CLKOUT signal to begin oscillating and it is preferable for
all LT8582 channels to have the same internal free running
frequency. Therefore, in general, use the same value R
T
resistor for all of the synchronized LT8582s.
EVENT BASED SEQUENCING
The PG pin may be used to sequence other ICs since it
is pulled low as long as the LT8582 is enabled and the
magnitude of the output voltage is below regulation (refer
to the Block Diagram). Since the PG pin is an open drain
output, it can be used to pull the SHDN pin of another IC
low until the output of one of the channels of the LT8582
LT8582
21
8582f
APPLICATIONS INFORMATION
is close to its regulation voltage. This method allows the
PG pin to disable multiple ICs. Refer to Figure 10 for the
necessary connections. Alternatively, the PG pin may be
used to pull the SS pin of another switching regulator low,
preventing the other regulator from switching.
The master switch, immune from the flying capaci-
tor current spike (seen only by the slave switch), can
therefore sense the inductor current more accurately.
Since the slave switch can sustain large current spikes,
the diodes that feed current into the flying capacitors do
not need current limiting resistors, leading to efficiency
and thermal improvements, as well as a smaller solution
size.
High V
OUT
Charge Pump Topology
The LT8582 can be used in a charge pump topology as
shown in Figure 11, multiplying the output of a boost
converter. The master switch (SWA) can be used to drive
the boost converter, while the slave switch (SWB) can
be used to drive one or more charge pump stages. This
topology is useful for high voltage applications including
VFD bias supplies.
Figure 10. Using the Two LT8582 Channels, with Power
Supply Sequencing
PG1
R
UVLO2
R
UVLO1
SET R
UVLO1
AND R
UVLO2
SUCH THAT
VIN1
UVLO
< VIN2
UVLO
SEE CONFIGURABLE UNDERVOLTAGE LOCKOUT
SECTION FOR DETAILS
10k
V
IN
SHDN
SYS
SHDN2SHDN1
LT8582
8582 F10
CH1
MASTER
CH2
SLAVE
CHARGE PUMP AIDED REGULATORS
Designing charge pumps with the LT8582 can offer efficient
solutions with fewer components than traditional circuits
because of the master/slave switch configuration on the
IC. Although the slave switch, SWB, operates in phase
with the master switch, SWA, only the current through the
master switch (SWA) is sensed by the current comparator
(A4 in the Block Diagram). This method of operation by
the master/slave switches can offer the following benefits
to charge pump designs:
The slave switch, by not performing a current sense
operation like the master switch, can sustain fairly
large current spikes without falsely tripping the current
comparator. In a charge pump, these spikes occur when
the flying capacitors charge up. Since this current spike
flows through SWB, it does not affect the operation of
the current comparator (A4 in the Block Diagram).
SSGND
SYNC
SWB
SWA
LT8582
CHx
8582 F11
PG
RT
V
IN
SHDN
CLKOUT
V
C
FBX
GATE
V
IN
9V TO 16V
100k
576k
80.6K
21k
22µH
383k
4.7µF
2.2µF
2.2µF
2.2µF
2.2µF
2.2µF 1.5nF
47pF
2.2µF
8.06k
2.2µF
V
OUT1
100V
80mA
V
OUT2
66V
120mA
Figure 11. High V
OUT
Charge Pump Topology

LT8582EDKD#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual 3A Boost/Inverting DC/DC Converter with Fault Protection
Lifecycle:
New from this manufacturer.
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