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16
Design Procedure
The design of an SMPS around a monolithic device does
not differ from that of a standard circuit using a controller
and a MOSFET. However, one needs to be aware of certain
characteristics specific of monolithic devices:
Figure 28. The Drain−Source Wave Shall Always be Positive . . .
1.004M 1.011M 1.018M 1.025M 1.032M
50.0
50.0
150
250
350
> 0 !!
1. In any case, the lateral MOSFET body−diode shall
never be forward biased, either during startup
(because of a large leakage inductance) or in
normal operation as shown by Figure 28.
As a result, the Flyback voltage which is reflected on the
drain at the switch opening cannot be larger than the input
voltage. When selecting components, you thus must adopt
a turn ratio which adheres to the following equation:
N · (Vout ) Vf) t Vin
min
(eq. 14)
. For instance, if
operating from a 120 V DC rail, with a delivery of 12 V, we
can select a reflected voltage of 100 Vdc maximum:
120–100 > 0. Therefore, the turn ratio Np:Ns must be
smaller than 100/(12 + 1) = 7.7 or Np:Ns < 7.7. We will see
later on how it affects the calculation.
2. A current−mode architecture is, by definition,
sensitive to subharmonic oscillations.
Subharmonic oscillations only occur when the
SMPS is operating in Continuous Conduction
Mode (CCM) together with a duty−cycle greater
than 50%. As a result, we recommend to operate
the device in DCM only, whatever duty−cycle it
implies (max = 65%). However, CCM operation
with duty−cycles below 40% is possible.
3. Lateral MOSFETs have a poorly dopped
body−diode which naturally limits their ability to
sustain the avalanche. A traditional RCD clamping
network shall thus be installed to protect the
MOSFET. In some low power applications,
a simple capacitor can also be used since
Vdrain max + Vin ) N · (Vout ) Vf) ) Ip ·
Lf
Ctot
Ǹ
(eq. 15)
, where Lf is the leakage inductance,
Ctot is the total capacitance at the drain node
(which is increased by the capacitor wired between
drain and source), N the Np:Ns turn ratio, Vout the
output voltage, Vf the secondary diode forward
drop and finally, Ip the maximum peak current.
Worse case occurs when the SMPS is very close to
regulation, e.g. the Vout target is almost reached
and Ip is still pushed to the maximum.
Taking into account all previous remarks, it becomes
possible to calculate the maximum power that can be
transferred at low line.
When the switch closes, Vin is applied across the primary
inductance Lp until the current reaches the level imposed by
the feedback loop. The duration of this event is called the ON
time and can be defined by:
ton +
Lp · Ip
Vin
(eq. 16)
At the switch opening, the primary energy is transferred
to the secondary and the flyback voltage appears across
Lp, resetting the transformer core with a slope of
N · (Vout ) Vf)
Lp
. toff, the OFF time is thus:
toff +
Lp · Ip
N · (Vout ) Vf)
(eq. 17)
If one wants to keep DCM only, but still need to pass the
maximum power, we will not allow a dead−time after the
core is reset, but rather immediately restart. The switching
time can be expressed by:
Tsw + toff ) ton + Lp · Ip ·
ǒ
1
Vin
)
1
N · (Vout ) Vf)
Ǔ
(eq. 18)
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17
The Flyback transfer formula dictates that:
Pout
h
+
1
2
·Lp·Ip
2
·Fsw
(eq. 19)
which, by extracting
Ip and plugging into Equation 19, leads to:
T
sw + Lp
2 · Pout
h ·Fsw·Lp
Ǹ
·
ǒ
1
Vin
)
1
N · (Vout ) Vf)
Ǔ
(eq. 20
)
Extracting Lp from Equation 20 gives:
Lp
critical
+
(Vin · Vr)
2
· h
2·Fsw·[Pout·(Vr
2
) 2·Vr·Vin) Vin
2
)]
(eq. 21)
, with Vr = N . (Vout + Vf) and h the efficiency.
If Lp critical gives the inductance value above which
DCM operation is lost, there is another expression we can
write to connect Lp, the primary peak current bounded by
the NCP101X and the maximum duty−cycle that needs to
stay below 50%:
Lpmax +
DCmax · Vinmin · Tsw
Ipmax
(eq. 22)
where Vinmin
corresponds to the lowest rectified bulk voltage, hence the
longest ton duration or largest duty−cycle. Ip max is the
available peak current from the considered part, e.g. 350 mA
typical for the NCP1013 (however, the minimum value of
this parameter shall be considered for reliable evaluation).
Combining Equations 21 and 22 gives the maximum
theoretical power you can pass respecting the peak current
capability of the NCP101X, the maximum duty−cycle and
the discontinuous mode operation:
Pmax :+ Tsw
2
· Vinmin
2
·Vr
2
· h ·
(eq. 23)
Fsw
(2 · Lpmax · Vr
2
) 4 · Lpmax · Vr · Vinmin
) 2 · Lpmax · Vinmin
2
)
From Equation 22 we obtain the operating duty−cycle
d +
Ip · Lp
Vin · Tsw
(eq. 24)
which lets us calculate the RMS
current circulating in the MOSFET:
IdRMS + Ip ·
d
3
Ǹ
(eq. 25)
. From this equation, we
obtain the average dissipation in the MOSFET:
Pavg +
1
3
·Ip
2
·d·R
DSon
(eq. 26)
to which switching
losses shall be added.
If we stick to Equation 23, compute Lp and follow the
above calculations, we will discover that a power supply
built with the NCP101X and operating from a 100 Vac line
minimum will not be able to deliver more than 7.0 W
continuous, regardless of the selected switching frequency
(however the transformer core size will go down as
Fswitching is increased). This number increases
significantly when operated from a single European mains
(18 W). Application note AND8125/D, “Evaluating the
Power Capability of the NCP101X Members” details how
to assess the available power budget from all the NCP101X
series.
Example 1. A 12 V 7.0 W SMPS operating on a large
mains with NCP101X:
Vin = 100 Vac to 250 Vac or 140 Vdc to 350 Vdc once
rectified, assuming a low bulk ripple
Efficiency = 80%
Vout = 12 V, Iout = 580 mA
Fswitching = 65 kHz
Ip max = 350 mA – 10% = 315 mA
Applying the above equations leads to:
Selected maximum reflected voltage = 120 V
with Vout = 12 V, secondary drop = 0.5 V Np:Ns = 1:0.1
Lp critical = 3.2 mH
Ip = 292 mA
Duty−cycle worse case = 50%
Idrain RMS = 119 mA
P
MOSFET
= 354 mW at R
DSon
= 24 W (T
J
> 100°C)
P
DSS
= 1.1 mA x 350 V = 385 mW, if DSS is used
Secondary diode voltage stress = (350 x 0.1) + 12 = 47 V
(e.g. a MBRS360T3, 3.0 A/60 V would fit)
Example 2. A 12 V 16 W SMPS operating on narrow
European mains with NCP101X:
Vin = 230 Vac " 15%, 276 Vdc for Vin min to 370 Vdc
once rectified
Efficiency = 80%
Vout = 12 V, Iout = 1.25 A
Fswitching = 65 kHz
Ip max = 350 mA – 10% = 315 mA
Applying the equations leads to:
Selected maximum reflected voltage = 250 V
with Vout = 12 V, secondary drop = 0.5 V Np:Ns = 1:0.05
Lp = 6.6 mH
Ip = 0.305 mA
Duty−cycle worse case = 0.47
Idrain RMS = 121 mA
P
MOSFET
= 368 mW at R
DSon
= 24 W (T
J
> 100°C)
P
DSS
= 1.1 mA x 370 V = 407 mW, if DSS is used below an
ambient of 50°C.
Secondary diode voltage stress = (370 x 0.05) + 12 = 30.5 V
(e.g. a MBRS340T3, 3.0 A/40 V)
Please note that these calculations assume a flat DC rail
whereas a 10 ms ripple naturally affects the final voltage
available on the transformer end. Once the Bulk capacitor has
been selected, one should check that the resulting ripple (min
Vbulk?) is still compatible with the above calculations. As an
example, to benefit from the largest operating range, a 7.0 W
board was built with a 47 mF bulk capacitor which ensured
discontinuous operation even in the ripple minimum waves.
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18
MOSFET Protection
As in any Flyback design, it is important to limit the
drain excursion to a safe value, e.g. below the MOSFET
BV
DSS
which is 700 V. Figure 29 presents possible
implementations:
Figure 29. Different Options to Clamp the Leakage Spike
+
NCP101X
C
Vcc
HV
1 8
2
3
4
7
5
+
CVcc
HV
Rclamp
Cclamp
D
1 8
2
3
4
7
5
+
CVcc
HV
D
1 8
2
3
4
7
5
+
C
Dz
ABC
NCP101X NCP101X
Figure 29A: The simple capacitor limits the voltage
according to Equation 15. This option is only valid for low
power applications, e.g. below 5.0 W, otherwise chances
exist to destroy the MOSFET. After evaluating the leakage
inductance, you can compute C with Equation 15. Typical
values are between 100 pF and up to 470 pF. Large
capacitors increase capacitive losses.
Figure 29B: This diagram illustrates the most standard
circuitry called the RCD network. Rclamp and Cclamp are
calculated using the following formulas:
Rclamp +
2 · Vclamp · (Vclamp * (Vout ) Vf sec) · N)
Lleak · Ip
2
·Fsw
(eq. 27)
Cclamp +
Vclamp
Vripple · Fsw · Rclamp
(eq. 28)
Vclamp is usually selected 50−80 V above the reflected
value N x (Vout + Vf). The diode needs to be a fast one and
a MUR160 represents a good choice. One major drawback
of the RCD network lies in its dependency upon the peak
current. Worse case occurs when Ip and Vin are maximum
and Vout is close to reach the steady−state value.
Figure 29C: This option is probably the most expensive of
all three but it offers the best protection degree. If you need
a very precise clamping level, you must implement a Zener
diode or a TVS. There are little technology differences
behind a standard Zener diode and a TVS. However, the die
area is far bigger for a transient suppressor than that of Zener.
A 5.0 W Zener diode like the 1N5388B will accept 180 W
peak power if it lasts less than 8.3 ms. If the peak current in
the worse case (e.g. when the PWM circuit maximum
current limit works) multiplied by the nominal Zener
voltage exceeds these 180 W, then the diode will be
destroyed when the supply experiences overloads. A
transient suppressor like the P6KE200 still dissipates 5.0 W
of continuous power but is able to accept surges up to 600 W
@ 1.0 ms. Select the Zener or TVS clamping level between
40 to 80 V above the reflected output voltage when the
supply is heavily loaded.

NCP1013ST130T3G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers Low Standby Power Monolithic Switcher
Lifecycle:
New from this manufacturer.
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