Data Sheet ADG1604
Rev. B | Page 15 of 20
ENABLE
DRIVE (V
IN
)
S1
D
GND
C
L
35pF
R
L
300Ω
V
OUT
A0
A1
S4
S3
S2
V
S
EN
V
DD
0.1µF
V
SS
V
DD
V
SS
0.1µF
V
IN
300Ω
t
OFF
(EN)
t
ON
(EN)
50% 50%
0.9V
OUT
0.9V
OUT
OUTPUT
0V
3V
V
OUT
0V
07982-025
Figure 31. Enable-to-Output Switching Delay
Sx D
V
S
GND
R
S
SW OFF
Q
INJ
= C
L
× Δ
V
OUT
SW OFF
SW ON
SW OFF
SW OFF
A2A1
EN
V
DD
V
SS
V
DD
DECODER
V
SS
V
OUT
V
OUT
V
IN
V
IN
Δ
V
OUT
C
L
1nF
07982-026
Figure 32. Charge Injection
ADG1604 Data Sheet
Rev. B | Page 16 of 20
TERMINOLOGY
I
DD
The positive supply current.
I
SS
The negative supply current.
V
D
(V
S
)
The analog voltage on Terminal D and Terminal S.
R
ON
The ohmic resistance between Terminal D and Terminal S.
R
FLAT(ON)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the specified
analog signal range.
I
S
(Off)
The source leakage current with the switch off.
I
D
(Off)
The drain leakage current with the switch off.
I
D
, I
S
(On)
The channel leakage current with the switch on.
V
INL
The maximum input voltage for Logic 0.
V
INH
The minimum input voltage for Logic 1.
I
INL
(I
INH
)
The input current of the digital input.
C
S
(Off)
The off switch source capacitance, which is measured with
reference to ground.
C
D
(Off)
The off switch drain capacitance, which is measured with
reference to ground.
C
D
, C
S
(On)
The on switch capacitance, which is measured with reference to
ground.
C
IN
The digital input capacitance.
t
TRANSITION
The delay time between the 50% and 90% points of the digital
input and switch on condition when switching from one address
state to another. See Figure 29.
t
ON
(EN)
The delay between applying the digital control input and the
output switching on. See Figure 31.
t
OFF
(EN)
The delay between applying the digital control input and the
output switching off. See Figure 31.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching. See Figure 32.
Off Isolation
A measure of unwanted signal coupling through an off switch.
See Figure 25.
Crosstalk
A measure of unwanted signal that is coupled through from
one channel to another as a result of parasitic capacitance. See
Figure 27.
Bandwidth
The frequency at which the output is attenuated by 3 dB. See
Figure 26.
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental. See Figure 28.
AC Power Supply Rejection Ratio (ACPSRR)
The ratio of the amplitude of signal on the output to the amplitude
of the modulation. This is a measure of the ability of the device
to avoid coupling noise and spurious signals that appear on the
supply voltage pin to the output of the switch. The dc voltage on the
device is modulated by a sine wave of 0.62 V p-p.
Data Sheet ADG1604
Rev. B | Page 17 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
061908-A
4.50
4.40
4.30
14
8
7
1
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65 BSC
0.15
0.05
0.30
0.19
1.20
MAX
1.05
1.00
0.80
0.20
0.09
0.75
0.60
0.45
COPLANARITY
0.10
SEATING
PLANE
Figure 33. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
COMPLIANT
TO
JED
EC S
TA
N
DA
RD
S
MO
-2
2
0-
WG
GC.
0
42709-A
1
0
.6
5
B
SC
B
OT
TO
M
VI
EW
T
OP
V
IE
W
1
6
5
8
9
12
13
4
E
XP
OS
ED
PA
D
P
IN 1
I
NDI
CA
TO
R
4.
10
4
.0
0 S
Q
3.
90
0
.5
0
0
.4
0
0.
30
SEA
TIN
G
PLANE
0
.8
0
0.75
0.
70
0.05 MAX
0
.
02
NO
M
0.
20 R
EF
C
OPLANARITY
0
.0
8
PIN
1
IN
D
IC
AT
O
R
0.
35
0.3
0
0
.2
5
2
.6
0
2
.50 S
Q
2
.
40
FOR PROPER CO
NNE
CTI
ON
OF
T
H
E E
X
PO
SE
D
PA
D, REFER TO
THE PIN
CONF
IG
UR
AT
I
ON
A
ND
F
UN
C
TI
ON DESCRIPTIONS
SEC
TIO
N O
F T
H
IS
DA
T
A S
HE
E
T.
Figure 34. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-16-26)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range Package Description Package Option
ADG1604BRUZ −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14
ADG1604BRUZ-REEL −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14
ADG1604BRUZ-REEL7 −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14
ADG1604BCPZ-REEL −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-26
ADG1604BCPZ-REEL7 40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-26
1
Z = RoHS Compliant Part.

ADG1604BRUZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Multiplexer Switch ICs 4:1 19MHz 950 mOhm CMOS
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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