LTC3805IMSE#TRPBF Datasheet LTC3805HMSE#PBF, LTC3805IDD#PBF, LTC3805EMSE#TRPBF | P13-P15

LTC3805

3805fg

Figure 4. Setting RUN Pin Voltage and Run/Stop Control

LTC3805

RUN

RUN/STOP

CONTROL

(OPTIONAL)

GND

3805 F04

applications inForMation

Leakage Inductance

Transformer leakage inductance (on either the primary

or secondary) causes a voltage spike to occur after the

MOSFET (Q1) turn-off. This is increasingly prominent at

higher load currents, where more stored energy must be

dissipated. In some cases an RC “snubber” circuit will be

required to avoid overvoltage breakdown at the MOSFET’s

drain node. Application Note 19 is a good reference on

snubber design. A bifilar or similar winding technique is a

good way to minimize troublesome leakage inductances.

However, remember that this will limit the primary-to-

secondary breakdown voltage, so bifilar winding is not

always practical.

Setting Undervoltage and Hysteresis on V

The RUN pin is connected to a resistive voltage divider

connected to V

as shown in Figure 4. The voltage thresh-

old for the RUN pin is V

RUNON

rising and V

RUNOFF

falling.

Note that V

RUNON

– V

RUNOFF

= 35mV of built-in voltage

hysteresis that helps eliminate false trips.

To introduce further user-programmable hysteresis, the

LTC3805 sources 5µA out of the RUN pin when operation

of LTC3805 is enabled. As a result, the falling threshold

for the RUN pin also depends on the value of R1 and can

be programmed by

the user. The falling threshold for V

is therefore

IN(RUN,FALLING)

= V

RUNOFF

•

− R1• 5µA

where R1(5µA) is the additional hysteresis introduced

by the 5µA current sourced by the RUN pin. When in

shutdown, the RUN pin does not source the 5µA current

and the rising threshold for V

is simply

IN(RUN,RISING)

= V

RUNON

•

External Run/Stop Control

To implement external run control, place a small N-channel

MOSFET from the RUN pin to GND as shown in Figure 4.

Drive the gate of this MOSFET high to pull the RUN pin

to ground and prevent converter operation.

Selecting Feedback Resistor Divider Values

The regulated output voltage is determined by the resistor

divider across V

OUT

(R3 and R4 in Figure 2). The ratio of R4

to R3 needed to produce a desired V

OUT

can be calculated:

R3 =

OUT

− 0.8V

0.8V

Choose resistance values for R3 and R4 to be as large as

possible in order to minimize any efficiency loss due to

the static current drawn from V

OUT

, but just small enough

so that when V

OUT

is in regulation the input current to the

pin is less than 1% of the current through R3 and R4.

A good rule of thumb is to choose R4 to be less than 80k.

LTC3805

3805fg

applications inForMation

Feedback in Isolated Applications

Isolated applications do not use the FB pin and error

amplifier but control the I

pin directly using an opto-

isolator driven on the other side of the isolation barrier as

shown in Figure 5. A detailed version is shown in Figure

9. For isolated converters, the FB pin is grounded which

provides pull-up on the I

pin. This pull-up is not enough

to properly bias the opto-isolator which is typically biased

using a resistor to V

. Since the I

pin cannot sink the

opto-isolator bias current, a diode is required to block

it from the I

pin. A low leakage Schottky diode or low

forward voltage PN junction diode should be used to

ensure that the opto-isolator is able to pull I

down to

its lower clamp.

Oscillator Synchronization

The oscillator may be synchronized to an external clock

by connecting the synchronization signal to the SYNC

pin. The LTC3805 oscillator and turn-on of the switch are

synchronized to the rising edge of the external clock. The

frequency of the external sync signal must be ±33% with

respect to f

OSC

(as programmed by R

). Additionally,

the value of f

SYNC

must be between 70kHz and 700kHz.

Current Sense Resistor Considerations

The external current sense resistor (R

SENSE

in Figure 2)

allows the user to optimize the current limit behavior for

the particular application. As the current sense resistor

is varied from several ohms down to tens of milliohms,

peak switch current goes from a fraction of an ampere

to several amperes. Care must be taken to ensure proper

circuit operation, especially with small current sense

resistor values.

For example, with the peak current sense voltage of 100mV

on the I

SENSE

pin, a peak switch current of 5A requires

a sense resistor of 0.020Ω. Note that the instantaneous

peak power in the sense resistor is 0.5W and it must be

rated accordingly. The LTC3805 has only a single sense

line to this resistor. Therefore, any parasitic resistance

in the ground side connection of the sense resistor will

increase its apparent value. In the case of a 0.020Ω sense

resistor, one milliohm of parasitic resistance will cause a

5% reduction in peak switch current. So the resistance of

printed circuit copper traces and vias cannot necessarily

be ignored.

Programmable Slope Compensation

The LTC3805 injects a ramping current through its I

SENSE

pin into an external slope compensation resistor R

SLOPE

This current ramp starts at zero right after the GATE pin

has been high for the LTC3805’s minimum duty cycle of

6%. The current rises linearly towards a peak of 10µA at

the maximum duty cycle of 80%, shutting off once the

GATE pin goes low. A series resistor R

SLOPE

connecting the

SENSE

pin to the current sense resistor R

SENSE

develops a

ramping voltage drop. From the perspective of the I

SENSE

pin, this ramping voltage adds to the voltage across the

sense resistor, effectively reducing the current comparator

threshold in proportion to duty cycle. This stabilizes the

control loop against subharmonic oscillation. The amount

of reduction in the current comparator threshold (∆V

SENSE

)

can be calculated using the following equation:

∆V

SENSE

DutyCycle − 6%

80%

10µA • R

SLOPE

Note: LTC3805 enforces 6% < Duty Cycle < 80%. A good

starting value for R

SLOPE

is 3k, which gives a 30mV drop

in current comparator threshold at 80% duty cycle.

Designs that do not operate at greater than 50% duty cycle

do not need slope compensation and may replace R

SLOPE

with a direct connection.

Figure 5. Circuit for Isolated Feedback

LTC3805

ISOLATION

BARRIER

GND

3805 F05

LTC3805

3805fg

Figure 6. Circuit to Decrease Overcurrent Threshold

LTC3805

GATE

SENSE

SLOPE

= 10µA

SLOPE

GND

3805 F06

applications inForMation

Overcurrent Threshold Adjustment

Figure 6 shows the connection of the overcurrent pin, OC,

along with the I

SENSE

pin and the current sense resistor

SENSE

located in the source circuit of the power NMOS

which is driven by the GATE pin. The internal overcurrent

threshold on the OC pin is set at V

OCT

= 100mV which is the

same as the peak current sense voltage V

I(MAX)

= 100mV on

the I

SENSE

pin. The role of the slope compensation adjust-

ment resistor R

SLOPE

and the slope compensation current

SLOPE

is discussed in the prior section. In combination

with the overcurrent threshold adjust current I

= 10µA,

an external resistor R

can be used to lower the overcur-

rent trip threshold from 100mV. This section describes

how to pick R

to achieve the desired performance. In the

discussion that follows be careful to distinguish between

“current limit” where the converter continues to run with

the I

SENSE

pin limiting current on a cycle-by-cycle basis

while the output voltage falls below the regulation point

and “overcurrent protection” where the OC pin senses an

overcurrent and shuts down the converter for a timeout

period before attempting an automatic restart.

One

overcurrent protection strategy is for the converter

never enter current limit but to maintain output volt-

age regulation up to the point of tripping the overcurrent

protection. Operation at minimum input voltage V

IN(MIN)

hits current limiting for the smallest output current and

is the design point for this strategy.

First, for operation at V

IN(MIN)

, calculate the duty cycle Duty

Cycle V

IN(MIN)

using the appropriate formula depending on

whether the converter is a boost, flyback or SEPIC. Then

use Duty Cycle V

IN(MIN)

to calculate ∆V

SENSE

(

VIN(MIN)

)

using the formula in the prior section. For overcurrent

protection to trip at exactly the point where current limit-

ing would begin set:

OC(CRIT)

∆V

SENSE VIN(MIN)

( )

10µA

To find the actual output current that trips overcurrent

protection, calculate the peak switch current I

(

VIN(MIN)

)

from:

PK VIN(MIN)

( )

100mV

− ∆

SENSE VIN(MIN)

( )

SENSE

Then calculate the converter output current that corre-

sponds to I

(

VIN(MIN)

)

. Again, the calculation depends

both on converter type and the details of converter design

including inductor current ripple. For minimum input volt-

age, R

OC(CRIT)

produces an overcurrent trip at an output

current just before loss of output voltage regulation and

the onset of current limiting. Note that the output current

that causes an overcurrent trip is higher for higher input

voltages but that an overcurrent trip will always occur

before loss of output voltage regulation. If desired to

meet a specific design target, an increase in R

above

OC(CRIT)

can be used to reduce the trip threshold and

make the converter trip for a lower output current.

This calculation is based on steady-state operation. De-

pending on design, overcurrent protection can also be

triggered during a start-up transient, particularly if large

output filter capacitors are being charged as output voltage

rises. If that is a problem, output capacitor charging can

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