CY7C68023-56LTXC Datasheet CY7C68023-56LTXC, CY7C68023-56LTXCT, CY7C68024-56LFXC | P1-P3

CY7C68023/CY7C68024

EZ-USB

NX2LP™ USB 2.0 NAND Flash

Controller

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-08055 Rev. *H Revised September 23, 2014

EZ-USB NX2LP™ USB 2.0 NAND Flash Controller

Features

■ High-Speed (480-Mbps) or Full-Speed (12-Mbps) USB support

■ Both common NAND page sizes supported

❐ 512 bytes — Up to 1 Gbit capacity

❐ 2K bytes — Up to 8 Gbit capacity

■ Eight chip enable pins

❐ Up to eight NAND flash single device chips

❐ Up to four NAND flash dual-device chips

■ Industry-standard ECC NAND flash correction

❐ 1-bit error correction per 256 bytes

❐ 2-bit error detection per 256 bytes

■ Industry-standard (SmartMedia) Page Management for Wear

Leveling Algorithm, Bad Block Handling, and Physical to

Logical management

■ Supports 8-bit NAND flash interfaces

■ Supports 30 ns, 50 ns, and 100 ns NAND flash timing

■ Complies with the USB Mass Storage Class Specification

Revision 1.0

■ CY7C68024 complies with the USB 2.0 Specification for

Bus-Powered Devices (TID# 40460274)

■ 43-mA typical active current

■ Space-saving and Pb-free 56-QFN package (8 mm × 8 mm)

■ Support for board-level manufacturing test through USB

interface

■ 3.3-V NAND flash operation

■ NAND flash power management support

Introduction

The EZ-USB NX2LPNX2LP implements a USB 2.0 NAND

Flash controller. This controller adheres to the Mass Storage

Class Bulk-Only Transport Specification. The USB port of the

NX2LP is connected to a host computer directly or through the

downstream port of a USB hub. The Host software issues

commands and data to the NX2LP and receives the status and

data from the NX2LP using the standard USB protocol.

The NX2LP supports industry-leading 8-bit NAND flash

interfaces and both common NAND page sizes of 512 and 2k

bytes. Eight chip enable pins allow the NX2LP to be connected

to up to eight single or four dual-device NAND flash chips.

Certain NX2LP features are configurable, enabling the NX2LP to

meet the needs of different design requirements.

USB 2.0

Xceiver

Smart HS/

FS USB

Engine

NAND Flash

Interface

Logic

8-bit Data Bus

NAND Control Signals

EZ-USB NX2LP

Internal Control Logic

PLL

24 MHz

Xtal

VBUS

D+

D-

Data

Control

Chip Reset

LED1#

LED2#

Write Protect

Chip Enable Signals

NX2LP Block Diagram

CY7C68023/CY7C68024

Document #: 38-08055 Rev. *H Page 2 of 10

Pin Assignments

Figure 1. 56-pin QFN

Pin Descriptions

Pin Name Type Default State at Startup Description

1 R_B1#

[1]

I Z Ready/Busy 1 (2.2k to 4k pull up resistor is required)

2 R_B2# I Z Ready/Busy 2 (2.2k to 4k pull up resistor is required)

3 AVCC PWR PWR Analog 3.3 V supply

4 XTALOUT Xtal N/A Crystal output

5 XTALIN Xtal N/A Crystal input

6 AGND GND GND Ground

7 AVCC PWR PWR Analog 3.3 V supply

8 DPLUS I/O Z USB D+

9 DMINUS I/O Z USB D-

10 AGND GND GND Ground

11 VCC PWR PWR 3.3 V supply

12 GND GND GND Ground

13 N/C N/A N/A No connect

14 GND GND GND Ground

15 Reserved N/A N/A Must be tied HIGH (no pull up resistor required)

Note

1. A # sign after the pin name indicates that it is an active LOW signal.

RESET#

GND

N/C

WP_SW#

Reserved

LED2#

LED1#

ALE

CLE

VCC

RE1#

RE0#

WE#

R_B1#

R_B2#

AVCC

XTALOUT

XTALIN

AGND

AVCC

DPLUS

DMINUS

AGND

VCC

GND

N/C

GND

Reserved

VCC

DD0

DD1

DD2

DD3

DD4

DD5

DD6

DD7

GND

VCC

GND

VCC

N/C

GND

CE7#

CE6#

CE5#

CE4#

CE3#

CE2#

CE1#

CE0#

Reserved

VCC

CY7C68023/CY7C68024

Document #: 38-08055 Rev. *H Page 3 of 10

16 Reserved N/A N/A Must be tied HIGH (no pull-up resistor required)

17 VCC PWR PWR 3.3 V supply

18 DDO I/O Z Data 0

19 DD1 I/O Z Data 1

20 DD2 I/O Z Data 2

21 DD3 I/O Z Data 3

22 DD4 I/O Z Data 4

23 DD5 I/O Z Data 5

24 DD6 I/O Z Data 6

25 DD7 I/O Z Data 7

26 GND GND GND Ground

27 VCC PWR PWR 3.3 V supply

28 GND GND GND Ground

29 WE# O H Write enable

30 RE0# O H Read Enable 0

31 RE1# O H Read Enable 1

32 VCC PWR PWR 3.3 V supply

33 CLE O Z Command latch enable

34 ALE O Z Address latch enable

35 LED1# O Z Data activity LED sink

36 LED2# O Z Chip active LED sink

37 Reserved O Z No Connect

38 WP_SW# I Z Write-protect switch input

39 N/C N/A N/A No connect

40 N/C N/A N/A No connect

41 GND GND GND Ground

42 RESET# I Z NX2LP chip reset

43 VCC PWR PWR 3.3 V supply

44 Reserved N/A N/A Must be tied HIGH

45 CE0# O Z Chip enable 0

46 CE1# O Z Chip enable 1

47 CE2# O Z Chip enable 2

48 CE3# O Z Chip enable 3

49 CE4# O Z Chip enable 4

50 CE5# O Z Chip enable 5

51 CE6# O Z Chip enable 6

52 CE7# O Z Chip enable 7

53 GND GND GND Ground

54 N/C N/A N/A No connect

55 VCC PWR PWR 3.3 V supply

56 GND GND GND Ground

Pin Descriptions (continued)

Pin Name Type Default State at Startup Description

P1-P3 P4-P6 P7-P9 P10-P10

CY7C68023-56LTXC

Mfr. #:

Buy CY7C68023-56LTXC

Manufacturer:

Cypress Semiconductor

Description:

Memory Controllers EZ-USB NX2LP NAND Flash Controller

Lifecycle:

New from this manufacturer.

Delivery:

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CY7C68023-56LTXC

CY7C68023-56LTXC

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