Data Sheet AD7798/AD7799
Rev. B | Page 9 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CS
AIN3(+)/P1
AIN3(–)/P2
AIN2(+)
AIN1(–)
AIN1(+)
SCLK
DOUT/RDY
DV
DD
AV
DD
REFIN(–)
AIN2(–) REFIN(+)
PSW
GND
DIN
AD7798/
AD7799
TOP VIEW
(Not to Scale)
04856-005
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 SCLK Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-triggered
input, making the interface suitable for opto-isolated applications. The serial clock can be continuous, with all data
transmitted in a continuous train of pulses. Alternatively, it can be noncontinuous, with the information transmitted
to or from the ADC in smaller batches of data.
CS
Chip Select Input. This is an active low logic input used to select the ADC.
CS
can be used to select the ADC in
systems with more than one device on the serial bus, or it can be used as a frame synchronization signal when
communicating with the device.
CS
can be hardwired low, allowing the ADC to operate in 3-wire mode, with SCLK,
DIN, and DOUT/
RDY
used to interface with the device.
3 AIN3(+)/P1 Analog Input/Digital Output Pin. AIN3(+) is the positive terminal of the differential analog input pair AIN3(+)/AIN3(−).
Alternatively, this pin can function as a general-purpose output bit referenced between AV
DD
and GND
4 AIN3(−)/P2 Analog Input/Digital Output Pin. AIN3(−) is the negative terminal of the differential analog input pair AIN3(+)/AIN3(−).
Alternatively, this pin can function as a general-purpose output bit referenced between AV
DD
and GND
5 AIN1(+) Analog Input. AIN1(+) is the positive terminal of the differential analog input pair AIN1(+)/AIN1(−).
6 AIN1(−) Analog Input. AIN1(−) is the negative terminal of the differential analog input pair AIN1(+)/AIN1(−).
7 AIN2(+) Analog Input. AIN2(+) is the positive terminal of the differential analog input pair AIN2(+)/AIN2(−).
8 AIN2(−) Analog Input. AIN2(−) is the negative terminal of the differential analog input pair AIN2(+)/AIN2(−).
9 REFIN(+) Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(−). REFIN(+) can lie
anywhere between AV
DD
and GND + 0.1 V. The nominal reference voltage (REFIN(+) – REFIN(−)) is 2.5 V, but the part
can function with a reference from 0.1 V to AV
DD
.
10 REFIN(−) Negative Reference Input. REFIN(−) is the negative reference input for REFIN. This reference input can lie anywhere
between GND and AV
DD
− 0.1 V.
11 PSW Low-Side Power Switch to GND.
12 GND Ground Reference Point.
13 AV
DD
Supply Voltage. 2.7 V to 5.25 V.
14 DV
DD
Digital Interface Supply Voltage. The logic levels for the serial interface pins are related to this supply, which is
between 2.7 V and 5.25 V. The DV
DD
voltage is independent of the voltage on AV
DD
; therefore, AV
DD
can equal 5 V
with DV
DD
at 3 V, or vice versa.
15 DOUT/
RDY
Serial Data Output/Data Ready Output. DOUT/
RDY
serves a dual purpose. It functions as a serial data output pin to
access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data
or control registers. In addition, DOUT/
RDY
operates as a data ready pin, going low to indicate the completion of a
conversion. If the data is not read after the conversion, the pin goes high before the next update occurs.
The DOUT/
RDY
falling edge can be used as an interrupt to a processor, indicating that valid data is available. With
an external serial clock, the data can be read using the DOUT/
RDY
pin. With
CS
low, the data/control word
information is placed on the DOUT/
RDY
pin on the SCLK falling edge and is valid upon the SCLK rising edge.
16 DIN Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers
within the ADC, with the register selection bits of the communication register identifying the appropriate register.
