LTC4266CGW#PBF Datasheet LTC4266CUHF#PBF, LTC4266IUHF#PBF, LTC4266IGW#PBF | P25-P27

LTC4266

4266ff

For more information www.linear.com/LTC4266

Four commonly available 1Ω resistors (0402 or larger

package size) can be used in parallel in place of a single

0.25Ω resistor. In order to meet the I

CUT

and I

LIM

accuracy

required by the IEEE specification, the sense resistors

should have ±1% tolerance or better, and no more than

±200ppm/°C temperature coefficient.

Output Cap

Each port requires a 0.22μF cap across its outputs to keep

the LTC4266 stable while in current limit during startup

or overload. Common ceramic capacitors often have sig-

nificant voltage coefficients; this means the capacitance

is reduced as the applied voltage increases. To minimize

this problem, X7R ceramic capacitors rated for at least

100V are recommended.

Surge Protection

Ethernet ports can be subject to significant cable surge

events. To keep PoE voltages below a safe level and protect

the application against damage, protection components,

as shown in Figure 19, are required at the main supply,

at the LTC4266 pins, and at each port.

Bulk transient voltage suppression (TVS

BULK

) and bulk

capacitance (C

BULK

) are required across the main PoE

supply and should be sized to accommodate system

level surge requirements. A large capacitance of 10μF or

greater (C3) is required across the +3.3V supply if V

is above AGND.

Each LTC4266 requires a 10Ω, 0805 resistor (R1) in series

from supply AGND to the LTC4266 AGND pin. Across the

LTC4266 AGND pin and V

pin are an SMAJ58A, 58V

TVS (D1) and a 1μF, 100V bypass capacitor (C1). These

components must be placed close to the LTC4266 pins.

If the V

supply is above AGND, each LTC4266 requires

a 10Ω, 0805 resistor (R2) in series from the +3.3V sup-

ply positive rail to the LTC4266 V

pin. Across the

LTC4266 V

pin and DGND pin are an SMAJ5.0A, 5.0V

TVS (D2) and a 0.1μF capacitor (C2). These components

must be placed close to the LTC4266 pins. DGND is tied

directly to the protected AGND pin. Pull-ups at the logic

pins should be to the protected side of the 10Ω resistors

at the V

pin. Pull-downs at the logic pins should be to

the protected side of the 10Ω resistors at the tied AGND

and DGND pins.

Finally, each port requires a pair of S1B clamp diodes, one

from OUTn to supply AGND (D3) and one from OUTn to

supply V

(D4). The diodes at the ports steer harmful

surges into the supply rails where they are absorbed by

the surge suppressors and the V

bypass capacitance.

The layout of these paths must be low impedance.

Further considerations include LTC4266 applications

with off-board connections, such as a daughter card to

a mother board or headers to an external supply or host

control board. Additional protection may be required at

the LTC4266 pins to these off-board connections.

LAYOUT GUIDELINES

Standard power layout guidelines apply to the LTC4266:

place the decoupling caps for the V

and V

supplies

near their respective supply pins, use ground planes, and

use wide traces wherever there are significant currents.

APPLICATIONS INFORMATION

Figure 19. LTC4274 Surge Protection

D4 S1B

OUT

0.22μF

100V

X7R

1µF

100V

X7R

SENSE GATE OUT

AUTO

SCL

SDAIN

DGND

AGND

1/4

LTC4266

–54V

4266 F19

S1B

OUTn

0.1µF

SMAJ5.0A

10Ω

10µF

BULK

TVS

BULK

+3.3V

SMAJ58A

10Ω

LTC4266

4266ff

For more information www.linear.com/LTC4266

APPLICATIONS INFORMATION

The main layout challenge involves the arrangement of

the current sense resistors, and their connections to the

LTC4266. Because the sense resistor values are very

low, layout parasitics can cause significant errors. Care

is required to achieve specified accuracy, particularly with

disconnect currents.

Figure 20 illustrates the problem. In the example on the

left, two ports have load currents I

and I

that return to

the V

power supply through a mutual resistance R

represents the combined resistances of any traces,

planes, and vias in the PCB that I

and I

share as they

return to the V

supply. The LTC4266 measures the volt-

age difference between its SENSE and V

pins to sense

the voltage drop across R

, but as the example shows,

introduces errors.

The example on the right shows how errors can be

minimized with a good layout. The circuit is rearranged

so that R

no longer affects V

, and the V

connection

to the LTC4266 is used as a Kelvin sense trace. V

not a perfect Kelvin connection because all four ports

controlled by the LTC4266 share the same sense trace,

and because the current through the trace (I

) is not zero.

However, as the equation shows, the remaining error is

a small offset term.

Figure 21 shows two LTC4266 chips controlling eight ports

(A though H). The ports are separated into two groups

of four; each has its own trace on the top PCB layer that

connects to the V

plane with a via. Currents from the U1

sub-circuit are effectively isolated from the U2 sub-circuit,

reducing the layout problem down to 4-port chunks; this

arrangement can be expanded for any number of ports.

Figure 22 shows an example of good 4-port layout. Each

0.25Ω sense resistor consists of four 1Ω resistors in

parallel. The four groups of resistors are arranged to

minimize the overlap in their current flows, which mini-

mizes mutual resistance. The horizontal slits cut in the

copper help to keep the currents separate. Wide copper

paths connect each group of resistors to the vias at the

center, so the resistance is very low.

Proper connection of the sense line is also important. In

Figure 22, U1 is not connected directly to the V

plane

but is connected instead to a Kelvin sense trace that

leads to the sense resistor array. Similarly, the via at the

center of the sense resistor array has a matching hole

in the V

plane. This arrangement prevents the mutual

resistance of the four large vias from influencing the

current measurements.

Figure 20. Layout Affects Current Readback Accuracy

MUTUAL RESISTANCE

4266 F20

– –

+ I

= I

+ I

LTC4266

GATE

SENSE

SIGNAL

SCALE ERROR

CROSSTALK ERROR

KELVIN SENSE LINE

= I

– I

+ I

LTC4266

GATE

SENSE

SIGNAL

SMALL OFFSET ERROR

LTC4266

4266ff

For more information www.linear.com/LTC4266

Figure 21. Layout Strategy to Reduce Mutual Resistance

LTC4266

PORTS A THROUGH D

SENSE1

SENSE2

SENSE3

SENSE4

VIA VIA

4266 F21

BY KEEPING THESE COPPER FILLS SEPARATE ON

THE SURFACE, MUTUAL RESISTANCE BETWEEN

PORTS A-D AND E-H IS ELIMINATED

THIS TRACE PROVIDES V

TO U1

BUT ALSO ACTS AS A KELVIN

SENSE LINE FOR PORTS A-D

COPPER FILL ON SURFACE LAYER

PLANE ON INNER LAYER

LTC4266

PORTS E THROUGH H

SENSE1

SENSE2

SENSE3

SENSE4

SENSE

RETURN TO

POWER SUPPLY

APPLICATIONS INFORMATION

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P32

LTC4266CGW#PBF

Mfr. #:

Buy LTC4266CGW#PBF

Manufacturer:

Analog Devices Inc.

Description:

Power Switch ICs - POE / LAN PoE+ 25.5W Quad PSE Controller

Lifecycle:

New from this manufacturer.

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LTC4266CGW#PBF

LTC4266CGW#PBF

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