MP3422—6.5A, 600KHZ HIGH EFFICIENCY, SYNCHRONOUS, STEP-UP CONVERTER WITH OUTPUT DISCONNECT IN 2X2MM QFN PACKAGE
MP3422 Rev.1.01 www.MonolithicPower.com 13
8/6/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
APPLICATION INFORMATION
COMPONENT SELECTION
Input Capacitor Selection
Low ESR input capacitors reduce input
switching noise and reduce the peak current
drawn from the battery. Ceramic capacitors are
a good choice for input decoupling and should
be located as close as possible to the device. A
ceramic capacitor larger than 22F is
recommended to restrain V
IN
ripple.
Output Capacitor Selection
The output capacitor requires a minimum
capacitance value of 22F at the programmed
output voltage to ensure stability over the full
operating range. A higher capacitance value
may be required to lower the output ripple and
also transient ripple. Low ESR capacitors such
as X5R or X7R type ceramic capacitors are
recommended. Supposing that ESR is zero, the
minimum output capacitor to support the ripple
in the PWM mode could be calculated by:
OOUT
MAX
IN
MIN
O
SOUT(MAX)
I(V V )
C
fV V
×−
≥
××
Where,
V
OUT(MAX)
= Maximum output voltage
V
IN(MIN)
= Minimum Input voltage
I
O
=Output current
f
S
= Switching frequency
V= Acceptable output ripple
A 1F ceramic capacitor is recommended
between the Out and PGnd pins. This reduces
spikes on the SW node and improves EMI
performance.
Inductor Selection
The MP3422 can utilize small surface mount
chip inductors due to its 600kHz switching
frequency. Inductor values between 1H and
2.2H are suitable for most applications. Larger
values of inductance will allow slightly greater
output current capability by reducing the
inductor ripple current, but larger value
inductance increases component size. The
minimum inductance value is given by:
IN(MIN) OUT(MAX) IN(MIN)
OUT(MAX) L S
V(V V)
L
VIf
×−
≥
×Δ ×
(3)
I
L
=Acceptable inductor current ripple
The inductor current ripple is typically set for
30% to 40% of the maximum inductor current.
The inductor should have low DCR (series
resistance of the inductor current without
saturating windings) to reduce the resistive
power loss. The saturated current (I
SAT
) should
be large enough to support the peak current.
PCB Layout Considerations
PCB layout for high frequency switching power
supplies can be critical. Poor layout can result
in reduced performance, excessive EMI,
resistive loss and system instability.
The steps below ensure good layout design.
1. The output capacitor must be placed as
close as possible to the OUT pin, with
minimal distance to PGND. A small
decoupling capacitor should be paralleled
with the bulk output capacitor and placed
as close as possible to the OUT Pin. This is
very important to reduce the spikes on the
SW Pin and improve EMI performance.
2. The input capacitor and inductor should as
close as possible to the IN and SW pins.
The trace between the inductor and the SW
pin should be wide and as short as
possible.
3. The feedback loop should be far away from
all noise sources such as the SW pin. The
feedback divider resistors should be as
close as possible to the FB and AGND pins.
4. The ground return of the input/output
capacitors should be tied as close as
possible to the PGND pin with a large
copper GND area. Vias around the GND
pin are recommended to lower the die
temperature.
5. INA pin must be connected to IN. NC pin
can either float or be connected to GND.
