74ABT2541CSJ

© 2005 Fairchild Semiconductor Corporation DS011502 www.fairchildsemi.com
September 1992
Revised March 2005
74ABT2541 Octal Buffer/Line Driver with 25: Series Resistors in the Outputs
74ABT2541
Octal Buffer/Line Driver with
25: Series Resistors in the Outputs
General Description
The ABT2541 is an octal buffer and line driver designed to
drive the capacitive inputs of MOS memory drivers,
address drivers, clock drivers, and bus-oriented transmit-
ters/receivers. Functionally identical to the ABT541.
The 25
series resistors in the outputs reduce ringing and
eliminate the need for external resistors.
Features
Guaranteed output skew
Guaranteed multiple output switching specifications
Output switching specified for both 50 pF and
250 pF loads
Guaranteed simultaneously switching noise level and
dynamic threshold performance
Guaranteed latchup protection
High impedance glitch free bus loading during entire
power up and power down cycle
Nondestructive hot insertion capability
Disable time less than enable time to avoid bus
contention
Ordering Code:
Devices also available in Tape and Reel. Specify by appending “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Schematic of Each Output
Pin Descriptions
Truth Table
H HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial
Z
High Impedance
Order Number Package Number Package Description
74ABT2541CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ABT2541CSJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT2541CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74ABT2541CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
OE
1
, OE
2
Output Enable Input (Active LOW)
I
0
I
7
Inputs
O
0
O
7
Outputs
Inputs Outputs
OE
1
OE
2
I
L L H H
H X X Z
X H X Z
L L L L
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74ABT2541
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Note 3: Guaranteed, but not tested.
Note 4: For 8 bit toggling, I
CCD
0.8 mA/MHz.
Storage Temperature 65 C to 150 C
Ambient Temperature under Bias
55 C to 125 C
Junction Temperature under Bias
55 C to 150 C
V
CC
Pin Potential to Ground Pin 0.5V to 7.0V
Input Voltage (Note 2)
0.5V to 7.0V
Input Current (Note 2)
30 mA to 5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State
0.5V to 5.5V
in the HIGH State
0.5V to V
CC
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
DC Latchup Source Current
500 mA
Over Voltage Latchup (I/O) 10V
Free Air Ambient Temperature
40 C to 85 C
Supply Voltage
4.5V to 5.5V
Minimum Input Edge Rate (
V/ t)
Data Input 50 mV/ns
Enable Input 20 mV/ns
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized LOW Signal
V
CD
Input Clamp Diode Voltage 1.2 V Min I
IN
18 mA
V
OH
Output HIGH Voltage 2.5 V Min I
OH
3 mA
2.0 V Min I
OH
32 mA
V
OL
Output LOW Voltage 0.8 V Min I
OL
15 mA
I
IH
Input HIGH Current 1 A MaxV
IN
2.7V (Note 3)
1V
IN
V
CC
I
BVI
Input HIGH Current 7 A MaxV
IN
7.0V
Breakdown Test
I
IL
Input LOW Current 1 A MaxV
IN
0.5V (Note 3)
1V
IN
0.0V
V
ID
Input Leakage Test 4.75 V 0.0 I
ID
1.9 A
All Other Pins Grounded
I
OZH
Output Leakage Current 10 A 0 5.5V V
OUT
2.7V; OE
n
2.0V
I
OZL
Output Leakage Current 10 A 0 5.5V V
OUT
0.5V; OE
n
2.0V
I
OS
Output Short-Circuit Current 100 275 mA Max V
OUT
0.0V
I
CEX
Output High Leakage Current 50 A MaxV
OUT
V
CC
I
ZZ
Bus Drainage Test 100 A 0.0V
OUT
5.5V; All Others GND
I
CCH
Power Supply Current 50 A Max All Outputs HIGH
I
CCL
Power Supply Current 30 mA Max All Outputs LOW
I
CCZ
Power Supply Current 50 A MaxOE
n
V
CC
;
All Others at V
CC
or GND
I
CCT
Additional I
CC
/Input Outputs Enabled 2.5 mA V
I
V
CC
2.1V
Outputs 3-STATE 2.5 mA Max Enable Input V
I
V
CC
2.1V
Outputs 3-STATE 50 A Data Input V
I
V
CC
2.1V
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
No Load mA/ Max Outputs OPEN
(Note 4) 0.1 MHz OE
n
GND (Note 3)
One Bit Toggling, 50% Duty Cycle
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74ABT2541
DC Electrical Characteristics
(SOIC Package)
Note 5: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 6: Max number of data inputs (n) switching. n-1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
).
Guaranteed, but not tested.
Note 7: Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
AC Electrical Characteristics
Extended AC Electrical Characteristics
(SOIC Package)
Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 11: The 3-STATE delays are dominated by the RC network (500
, 250 pF) on the output and have been excluded from the datasheet.
Symbol Parameter Min Typ Max Units
V
CC
Conditions
C
L
50 pF, R
L
500
V
OLP
Quiet Output Maximum Dynamic V
OL
0.6 0.8 V 5.0 T
A
25 C (Note 5)
V
OLV
Quiet Output Minimum Dynamic V
OL
0.5 0.4 V 5.0 T
A
25 C (Note 5)
V
OHV
Minimum HIGH Level Dynamic Output Voltage 2.7 3.1 V 5.0 T
A
25 C (Note 6)
V
IHD
Minimum HIGH Level Dynamic Input Voltage 2.0 1.4 V 5.0 T
A
25 C (Note 7)
V
ILD
Maximum LOW Level Dynamic Input Voltage 1.2 0.8 V 5.0 T
A
25 C (Note 7)
Symbol Parameter
T
A
25 CT
A
40 C to 85 C
Units
V
CC
5V V
CC
4.5V–5.5V
C
L
50 pF C
L
50 pF
Min Typ Max Min Max
t
PLH
Propagation Delay Data to Outputs 1.0 2.3 3.6 1.0 3.6
ns
t
PHL
1.0 3.3 4.1 1.0 4.1
t
PZH
Output Enable Time 1.5 3.7 6.0 1.5 6.0
ns
t
PZL
1.5 4.3 6.5 1.5 6.5
t
PHZ
Output Disable Time 1.0 3.5 6.0 1.0 6.0
ns
t
PLZ
1.0 3.7 5.6 1.0 5.6
Symbol Parameter
40 C to 85 C
T
A
40 C to 85 CT
A
40 C to 85 C
Units
V
CC
4.5V–5.5V V
CC
4.5V–5.5V V
CC
4.5V–5.5V
C
L
50 pF C
L
250 pF C
L
250 pF
8 Outputs Switching 1 Output Switching 8 Outputs Switching
(Note 8) (Note 9) (Note 10)
Min Typ Max Min Max Min Max
f
TOGGLE
Maximum Toggle Frequency 100 MHz
t
PLH
Propagation Delay 1.5 5.0 1.5 6.0 2.5 8.5
ns
t
PHL
Data to Outputs 1.5 5.5 1.5 10.0 2.5 11.0
t
PZH
Output Enable Time 1.5 6.5 2.5 7.5 2.5 9.5
ns
t
PZL
1.5 7.0 2.5 11.0 2.5 12.5
t
PHZ
Output Disable Time 1.0 6.0
(Note 11) (Note 11) ns
t
PLZ
1.0 6.0

74ABT2541CSJ

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Buffers & Line Drivers Octal Buf/Line Drv
Lifecycle:
New from this manufacturer.
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