W256
Document #: 38-07256 Rev. *C Page 4 of 9
Maximum Ratings
Supply Voltage to Ground Potential..................–0.5 to +7.0V
DC Input Voltage (except BUF_IN)............–0.5V to V
DD
+0.5
Storage Temperature ..................................–65°C to +150°C
Static Discharge Voltage............................................>2000V
(per MIL-STD-883, Method 3015)
Operating Conditions
[2]
Parameter Description Min. Typ. Max. Unit
V
DD3.3
Supply Voltage 3.135 3.465 V
V
DD2.5
Supply Voltage 2.375 2.625 V
T
A
Operating Temperature (Ambient Temperature) 0 70 °C
C
OUT
Output Capacitance 6 pF
C
IN
Input Capacitance 5 pF
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Typ. Max. Unit
V
IL
Input LOW Voltage For all pins except SMBus 0.8 V
V
IH
Input HIGH Voltage 2.0 V
I
IL
Input LOW Current V
IN
= 0V 50 µA
I
IH
Input HIGH Current V
IN
= V
DD
50 µA
I
OH
Output HIGH Current V
DD
= 2.375V
V
OUT
= 1V
–18 –32 mA
I
OL
Output LOW Current V
DD
= 2.375V
V
OUT
= 1.2V
26 35 mA
V
OL
Output LOW Voltage
[3]
I
OL
= 12 mA, V
DD
= 2.375V 0.6 V
V
OH
Output HIGH Voltage
[3]
I
OH
= –12 mA, V
DD
= 2.375V 1.7 V
I
DD
Supply Current
[3]
(DDR-Only mode)
Unloaded outputs, 133 MHz 400 mA
I
DD
Supply Current
(DDR-Only mode)
Loaded outputs, 133 MHz 500 mA
I
DDS
Supply Current PWR_DWN# = 0 100 µA
V
OUT
Output Voltage Swing See Test Circuity (Refer to
Figure 1)
0.7 V
DD
+ 0.6 V
V
OC
Output Crossing Voltage (V
DD
/2)
–0.1
V
DD
/2 (V
DD
/2)
+0.1
V
IN
DC
Input Clock Duty Cycle 48 52 %
Notes:
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
W256
Document #: 38-07256 Rev. *C Page 5 of 9
Switching Characteristics
[4]
Parameter Name Test Conditions Min. Typ. Max. Unit
Operating Frequency 66 180 MHz
Duty Cycle
[4,5]
= t
2
÷ t
1
Measured at 1.4V for 3.3V outputs
Measured at VDD/2 for 2.5V outputs.
IN
DC
–5%
IN
DC
+5% %
t
3
SDRAM Rising Edge Rate
[4]
Measured between 0.4V and 2.4V 1.0 2.50 V/ns
t
4
SDRAM Falling Edge Rate
[4]
Measured between 2.4V and 0.4V 1.0 2.50 V/ns
t
3d
DDR Rising Edge Rate
[4]
Measured between 20% to 80% of
output (Refer to Figure 1)
0.5 1.50 V/ns
t
4d
DDR Falling Edge Rate
[4]
Measured between 20% to 80% of
output (Refer to Figure 1)
0.5 1.50 V/ns
t
5
Output to Output Skew
[4]
All outputs equally loaded 100 ps
t
6
Output t4o Output Skew for
SDRAM
[2]
All outputs equally loaded 150 ps
t
7
SDRAM Buffer HH Prop. Delay
[4]
Input edge greater than 1 V/ns 5 10 ns
t
8
SDRAM Buffer LLProp. Delay
[4]
Input edge greater than 1 V/ns 5 10 ns
Switching Waveforms
Notes:
4. All parameters specified with loaded outputs.
5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/ns.
Duty Cycle Timing
t
1
t
2
All Outputs Rise/Fall Time
OUTPUT
t
3
3.3V
0V
0.4V
2.4V 2.4V
0.4V
t
4
Output-Output Skew
t
5
OUTPUT
OUTPUT
W256
Document #: 38-07256 Rev. *C Page 6 of 9
Figure 1 shows the differential clock directly terminated by a
120 resistor.
Switching Waveforms (continued)
SDRAM Buffer HH and LL Propagation Delay
t
6
INPUT
OUTPUT
t
7
1.5V
1.5V
)
)
R
T
=120
Receiver
60
60
V
C
C
V
CC
Device
Under
Test
Figure 1. Differential Signal Using Direct Termination Resistor
Out
Out
VTR
VCP

W256H

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC CLK BUFFER 1:12 180MHZ 28SSOP
Lifecycle:
New from this manufacturer.
Delivery:
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