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13
+
-
+
-
S
R
+
R
R
R
2R
V
Clamp
[
1.67
ǒ
R
2
R
1
) 1
Ǔ
I
pk(max)
[
V
Clamp
R
S
5.0V Ref
Q
Bias
Osc
EA
1.0V
5(9)
7(11)
6(10)
5(8)
3(5)
R
S
Q1
V
CC
V
in
1(1)
2(3)
4(7)
8(14)
R
1
V
Clamp
R
2
Where: 0 V
Clamp
1.0 V
C
MPSA63
t
Soft
Start
+*In
ƪ
1 *
V
C
3V
Clamp
ƫ
C
R
1
R
2
R
1
)R
2
7(12)
1.0 mA
Comp/Latch
5.0V Ref
+
-
S
R
Q
Bias
+
1.0mA
Osc
R
R
R
2R
EA
1.0V
5(9)
1(1)
2(3)
4(7)
8(14)
C
1.0M
t
Soft-Start
3600C in mF
Figure 25. SoftStart Circuit Figure 26. Adjustable Buffered Reduction of
Clamp Level with SoftStart
+
-
5.0V Ref
+
-
S
R
Q
(11)
(10)
(8)
Comp/Latch
(5)
R
S
1/4 W
V
CC
V
in
K
M
D
SENSEFET
G
S
Power Ground:
To Input Source
Return
Control Circuitry Ground:
To Pin (9)
Virtually lossless current sensing can be achieved with the implementation of a
SENSEFET power switch. For proper operation during over-current conditions, a
reduction of the I
pk(max)
clamp level must be implemented. Refer to Figures 24 and 26.
V
Pin 5
[
R
S
I
pk
r
DS(on)
r
DM(on)
) R
S
If: SENSEFET = MTP10N10M
R
S
= 200
Then : V
Pin5
[ 0.075I
pk
(12)
Figure 27. Current Sensing Power MOSFET
+
-
5.0V Ref
+
-
S
R
Q
7(11)
6(10)
5(8)
3(5)
R
S
Q1
V
CC
V
in
C
R
The addition of the RC filter will eliminate instability caused by the leading
edge spike on the current waveform.
7(12)
Comp/Latch
Figure 28. Current Waveform Spike Suppression
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Figure 29. MOSFET Parasitic Oscillations
6(10)
5(8)
3(5)
R
S
Q1
V
in
C1
Base Charge
Removal
The totem pole output can furnish negative base current for enhanced
transistor turn-off, with the addition of capacitor C
1
.
S
R
5.0V Ref
Q
7(11)
6(10)
5(8)
3(5)
R
S
Q1
V
CC
I
B
+
-
0
V
in
Isolation
Boundary
V
GS
Waveforms
+
-
0
+
-
0
50% DC 25% DC
I
p
k +
V
(Pin1)
* 1.4
3R
S
ǒ
N
S
N
p
Ǔ
Comp/Latch
7(12)
R
C
N
S
N
P
+
-
+
-
Bias
+
Osc
R
R
R
2R
EA
5(9)
1(1)
2(3)
4(7)
8(14)
The MCR101 SCR must be selected for a holding of < 0.5 mA @ T
A(min)
. The simple two
transistor circuit can be used in place of the SCR as shown. All resistors are 10 k.
MCR
101
2N
3905
2N
3903
1.0 mA
S
R
5.0V Ref
Q
7(11)
6(10)
5(8)
3(5)
R
S
Q1
V
CC
V
in
Series gate resistor R
g
will damp any high frequency parasitic oscillations
caused by the MOSFET input capacitance and any series wiring inductance in
the gate-source circuit.
7(12)
R
g
Comp/Latch
+
-
+
-
Figure 30. Bipolar Transistor Drive
Figure 31. Isolated MOSFET Drive Figure 32. Latched Shutdown
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+
-
+
-
5.0V Ref
36V
S
R
Q
Bias
+
1.0mA
Osc
R
R
R
2R
EA
1.0V
7(12)
7(11)
6(10)
5(8)
3(5)
R
S
V
CC
V
in
1(1)
2(3)
4(7)
8(14)
R
T
C
T
The buffered oscillator ramp can be resistively summed with either the voltage
feedback or current sense inputs to provide slope compensation.
m
- 3.0m
-m
R
f
C
f
R
i
R
d
From V
O
R
Slope
MPS3904
5(9)
Comp/Latch
Figure 33. Error Amplifier Compensation
+
R
2R
1.0mA
EA
2(3)
5(9)
2.5V
1(1)
R
f
C
f
R
d
R
i
From V
O
Error Amp compensation circuit for stabilizing any current mode topology except for boost and flyback
converters operating with continuous inductor current.
R
f
8.8 k
+
R
2R
1.0mA
EA
2(3)
5(9)
2.5V
1(1)
R
f
C
f
R
d
R
p
From V
O
Error Amp compensation circuit for stabilizing current mode boost and flyback
topologies operating with continuous inductor current.
C
p
R
i
Figure 34. Slope Compensation

UC2842BDR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers PWM CONTROLLER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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