Features
Fast Read Access Time – 55 ns
Dual Voltage Range Operation
Low-voltage Power Supply Range, 3.0V to 3.6V
or Standard 5V ± 10% Supply Range
Pin Compatible with JEDEC Standard AT27C256R
Low-power CMOS Operation
20 µA Max (Less than 1 µA Typical) Standby for V
CC
= 3.6V
29 mW Max Active at 5 MHz for V
CC
= 3.6V
JEDEC Standard Packages
32-lead PLCC
28-lead SOIC
28-lead TSOP
High-reliability CMOS Technology
2,000V ESD Protection
200 mA Latchup Immunity
Rapid Programming Algorithm – 100 µs/Byte (Typical)
CMOS and TTL Compatible Inputs and Outputs
JEDEC Standard for LVTTL
Integrated Product Identification Code
Industrial Temperature Range
Green (Pb/Halide-free) Packaging Option
1. Description
The AT27LV256A is a high-performance, low-power, low-voltage 262,144-bit one-
time programmable read-only memory (OTP EPROM) organized as 32K by 8 bits. It
requires only one supply in the range of 3.0V to 3.6V in normal read mode operation,
making it ideal for fast, portable systems using battery power.
Atmel’s innovative design techniques provide fast speeds that rival 5V parts while
keeping the low power consumption of a 3.3V supply. At V
CC
= 3.0V, any byte can be
accessed in less than 55 ns. With a typical power dissipation of only 18 mW at 5 MHz
and V
CC
= 3.3V, the AT27LV256A consumes less than one fifth the power of a stan-
dard 5V EPROM. Standby mode supply current is typically less than 1 µA at 3.3V.
The AT27LV256A is available in industry-standard JEDEC-approved one-time
programmable (OTP) plastic PLCC, SOIC and TSOP packages. All devices feature
two-line control (CE
, OE) to give designers the flexibility to prevent bus contention.
The AT27LV256A operating with V
CC
at 3.0V produces TTL level outputs that are
compatible with standard TTL logic devices operating at V
CC
= 5.0V. The device is
also capable of standard 5-volt operation making it ideally suited for dual supply range
systems or card products that are pluggable in both 3-volt and 5-volt hosts.
Atmel’s AT27LV256A has additional features to ensure high quality and efficient pro-
duction use. The Rapid Programming Algorithm reduces the time required to program
the part and guarantees reliable programming. Programming time is typically only
100 µs/byte. The Integrated Product Identification Code electronically identifies the
device and manufacturer. This feature is used by industry-standard programming
equipment to select the proper programming algorithms and voltages. The
AT27LV256A programs exactly the same way as a standard 5V AT27C256R and
uses the same programming equipment.
256K (32K x 8)
Low-voltage
OTP EPROM
AT27LV256A
0547G–EPROM–12/07
2
0547G–EPROM–12/07
AT27LV256A
2.1 28-lead SOIC Top View
2.2 32-lead PLCC Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VPP
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
VCC
A14
A13
A8
A9
A11
OE
A10
CE
O7
O6
O5
O4
O3
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A6
A5
A4
A3
A2
A1
A0
NC
O0
A8
A9
A11
NC
OE
A10
CE
O7
O6
4
3
2
1
32
31
30
14
15
16
17
18
19
20
O1
O2
GND
NC
O3
O4
O5
A7
A12
VPP
NC
VCC
A14
A13
2.3 28-lead TSOP (Type 1) Top View
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
OE
A11
A9
A8
A13
A14
VCC
VPP
A12
A7
A6
A5
A4
A3
A10
CE
O7
O6
O5
O4
O3
GND
O2
O1
O0
A0
A1
A2
Note: 1. PLCC Package Pins 1 and 17 are Don’t Connect.
2. Pin Configurations
Pin Name Function
A0 - A14 Addresses
O0 - O7 Outputs
CE
Chip Enable
OE
Output Enable
NC No Connect
3
0547G–EPROM–12/07
AT27LV256A
3. System Considerations
Switching between active and standby conditions via the Chip Enable pin may produce tran-
sient voltage excursions. Unless accommodated by the system design, these transients may
exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high
frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This
capacitor should be connected between the V
CC
and Ground terminals of the device, as close
to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit
boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again
connected between the V
CC
and Ground terminals. This capacitor should be positioned as
close as possible to the point where the power supply is connected to the array.
4. Block Diagram
Note: 1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is
V
CC
+ 0.75V DC which may be exceeded if certain precautions are observed (consult application notes) and which may
overshoot to +7.0V for pulses of less than 20 ns.
5. Absolute Maximum Ratings*
Temperature Under Bias.................................. -40°C to +85°C
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Storage Temperature..................................... -65°C to +125°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
(1)
Voltage on A9 with
Respect to Ground ......................................-2.0V to +14.0V
(1)
V
PP
Supply Voltage with
Respect to Ground .......................................-2.0V to +14.0V
(1)

AT27LV256A-90RU

Mfr. #:
Manufacturer:
Description:
IC EPROM 256K PARALLEL 28SOIC
Lifecycle:
New from this manufacturer.
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