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NBXDBA009LNHTAG

P1-P3P4-P6
© Semiconductor Components Industries, LLC, 2009
October, 2009 − Rev. 2
1 Publication Order Number:
NBXDBA009/D
NBXDBA009
3.3 V, 75 MHz / 150 MHz
LVPECL Clock Oscillator
The NBXDBA009 dual frequency crystal oscillator (XO) is
designed to meet today’s requirements for 3.3 V LVPECL clock
generation applications. The device uses a high Q fundamental crystal
and Phase Lock Loop (PLL) multiplier to provide selectable 75 MHz
or 150 MHz, ultra low jitter and phase noise LVPECL differential
output.
This device is a member of ON Semiconductor’s PureEdget clock
family that provides accurate and precision clock solutions.
Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape
and reel in quantities of 1000.
Features
• LVPECL Differential Output
• Uses High Q Fundamental Mode Crystal and PLL Multiplier
• Ultra Low Jitter and Phase Noise − 0.4 ps (12 kHz − 20 MHz)
• Selectable Output Frequency − 75 MHz (default) / 150 MHz
• Hermetically Sealed Ceramic SMD Package
• RoHS Compliant
• Operating Range 3.3 V ±10%
• Total Frequency Stability − $50 PPM
• This is a Pb−Free Device
Applications
• SAS Gen2
• Serial ATA
Figure 1. Simplified Logic Diagram
PLL
Clock
Multiplier
Crystal
GNDFSELOE
CLK CLKV
DD
654
123
http://onsemi.com
Device Package Shipping
†
ORDERING INFORMATION
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
NBXDBA009LN1TAG CLCC−6
(Pb−Free)
1000/
Tape & Reel
MARKING DIAGRAM
NBXDBA009 = NBXDBA009 (±50 PPM)
75/150 = Output Frequency (MHz)
AA = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
6 PIN CLCC
LN SUFFIX
CASE 848AB
NBXDBA009
75/150
AAWLYYWWG
NBXDBA009LNHTAG CLCC−6
(Pb−Free)
100/
Tape & Reel
NBXDBA009
http://onsemi.com
2
FSEL
OE
GND
CLK
V
DD
CLK
1
2
3
6
5
4
Figure 2. Pin Connections (Top View)
Table 1. PIN DESCRIPTION
Pin No. Symbol I/O Description
1 OE LVTTL/LVCMOS
Control Input
Output Enable Pin. When left floating pin defaults to logic HIGH and output is active.
See OE pin description Table 2.
2 FSEL LVTTL/LVCMOS
Control Input
Output Frequency Select Pin. Pin will default to logic HIGH when left open. See Output
Frequency Select pin description Table 3.
3 GND Power Supply Ground 0 V
4 CLK LVPECL Output
Non−Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to
V
TT
= V
DD
− 2 V.
5 CLK LVPECL Output
Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to
V
TT
= V
DD
− 2 V.
6 V
DD
Power Supply Positive power supply voltage. Voltage should not exceed 3.3 V ±10%.
Table 2. OUTPUT ENABLE TRI−STATE FUNCTION
OE Pin Output Pins
Open Active
HIGH Level Active
LOW Level High Z
Table 3. OUTPUT FREQUENCY SELECT
FSEL Pin Output Frequency (MHz)
Open
(pin will float high)
75
HIGH Level 75
LOW Level 150
Table 4. ATTRIBUTES
Characteristic Value
Input Default State Resistor
170 kW
ESD Protection Human Body Model
Machine Model
2 kV
200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Table 5. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Units
V
DD
Positive Power Supply GND = 0 V 4.6 V
I
out
LVPECL Output Current Continuous
Surge
25
50
mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −55 to +120 °C
T
sol
Wave Solder See Figure 6 260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NBXDBA009
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3
Table 6. DC CHARACTERISTICS (V
DD
= 3.3 V ± 10%, GND = 0 V, T
A
= −40°C to +85°C) (Note 2)
Symbol
Characteristic Conditions Min. Typ. Max. Units
I
DD
Power Supply Current 79 100 mA
V
IH
OE and FSEL Input HIGH Voltage 2000 V
DD
mV
V
IL
OE and FSEL Input LOW Voltage GND − 300 800 mV
I
IH
Input HIGH Current OE
FSEL
−100
−100
+100
+100
mA
I
IL
Input LOW Current OE
FSEL
−100
−100
+100
+100
mA
V
OH
Output HIGH Voltage
V
DD
= 3.3 V
V
DD
−1195
2105
V
DD
−945
2355
mV
V
OL
Output LOW Voltage
V
DD
= 3.3 V
V
DD
−1945
1355
V
DD
−1600
1700
mV
V
OUTPP
Output Voltage Amplitude 660 mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Measurement taken with outputs terminated with 50 ohm to V
DD
−2 V. See Figure 5.
Table 7. AC CHARACTERISTICS (V
DD
= 3.3 V ± 10%, GND = 0 V, T
A
= −40°C to +85°C) (Note 3)
Symbol Characteristic Conditions Min. Typ. Max. Units
f
CLKOUT
Output Clock Frequency
FSEL = HIGH 75
MHz
FSEL = LOW 150
Df
Frequency Stability − NBXDBA009 (Note 4) ±50 ppm
F
NOISE
Phase−Noise Performance 100 Hz of Carrier −108/−102 dBc/Hz
f
CLKout
= 75 MHz/150 MHz
(See Figures 3 and 4)
1 kHz of Carrier −122/−11 6 dBc/Hz
10 kHz of Carrier −129/−122 dBc/Hz
100 kHz of Carrier −129/−122 dBc/Hz
1 MHz of Carrier −137/−131 dBc/Hz
10 MHz of Carrier −161/−158 dBc/Hz
t
jit
(F)
RMS Phase Jitter 12 kHz to 20 MHz 0.4 0.9 ps
t
jitter
Cycle to Cycle, RMS 1000 Cycles 2.3 8 ps
Cycle to Cycle, Peak−to−Peak 1000 Cycles 13 30 ps
Period, RMS 10,000 Cycles 1.3 4 ps
Period, Peak−to−Peak 10,000 Cycles 8.7 20 ps
t
OE/OD
Output Enable/Disable Time 200 ns
t
DUTY_CYCLE
Output Clock Duty Cycle
(Measured at Cross Point)
48 50 52 %
t
R
Output Rise Time (20% and 80%) 250 400 ps
t
F
Output Fall Time (80% and 20%) 250 400 ps
t
start
Start−up Time 1 5 ms
Aging
1
st
Year 3 ppm
Every Year After 1
st
1 ppm
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Measurement taken with outputs terminated with 50 ohm to V
DD
−2 V. See Figure 5.
4. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration, and first year aging.
P1-P3P4-P6

NBXDBA009LNHTAG

Mfr. #:
Buy NBXDBA009LNHTAG
Manufacturer:
ON Semiconductor
Description:
Clock Drivers & Distribution 3.3V 75/150MHZ LVPECL CLK
Lifecycle:
New from this manufacturer.
Delivery:
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