MAX1082/MAX1083
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 10-Bit ADCs with Internal Reference
16
Maxim Integrated
mode (PD1 = PD0 = 0), with an external reference and
conversion controlled at the maximum clock speed.
One dummy conversion to power up the device is
needed, but no waiting time is necessary to start the
second conversion, thereby achieving lower power
consumption at up to half the full sampling rate.
Using Fast Power-Down and Reduced
Power Modes
FASTPD and REDP modes achieve the lowest power
consumption at speeds close to the maximum sam-
pling rate. Figure 10 shows the MAX1083’s power con-
sumption in FASTPD mode (PD1 = 0, PD0 = 1), REDP
mode (PD1 = 1, PD0 = 0), and, for comparison, normal
operating mode (PD1 = 1, PD0 = 1). The figure shows
power consumption using the specified power-down
mode, with the internal reference and conversion con-
trolled at the maximum clock speed. The clock speed
in FASTPD or REDP should be limited to 4.8MHz for the
MAX1082/MAX1083. FULLPD mode may provide
increased power savings in applications where the
MAX1082/MAX1083 are inactive for long periods of
time, but intermittent bursts of high-speed conversions
are required.
Internal and External References
The MAX1082/MAX1083 can be used with an internal
or external reference voltage. An external reference
can be connected directly at REF or at the REFADJ pin.
An internal buffer is designed to provide 2.5V at
REF for the MAX1082/MAX1083. The internally trimmed
1.22V reference is buffered with a 2.05 gain.
Internal Reference
The MAX1082/MAX1083’s full-scale range with the
internal reference is 2.5V with unipolar inputs and
±1.25V with bipolar inputs. The internal reference volt-
age is adjustable by ±100mV with the circuit in Figure
12.
External Reference
The MAX1082/MAX1083’s external reference can be
placed at the input (REFADJ) or the output (REF) of the
internal reference-buffer amplifier. The REFADJ input
impedance is typically 17k. At REF, the DC input
resistance is a minimum of 18k. During conversion, an
external reference at REF must deliver up to 350µA DC
load current and have 10 or less output impedance. If
the reference has a higher output impedance or is
noisy, bypass it close to the REF pin with a 4.7µF
capacitor.
To use the direct REF input, disable the internal buffer
by connecting REFADJ to V
DD1
. Using the REFADJ
input makes buffering the external reference unneces-
sary.
Transfer Function
Table 5 shows the full-scale voltage ranges for unipolar
and bipolar modes.
Figure 13 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 14 shows the bipolar
I/O transfer function. Code transitions occur halfway
between successive-integer LSB values. Output coding
is binary, with 1LSB = 2.44mV (2.500V/2/1024) for
t
CSW
t
CP
t
CSH
t
CS1
t
STD
t
DOD
t
DOV
t
DOH
t
STV
t
STH
#10
SCLK
DIN
DOUT
SSTRB
t
CSS
t
CH
t
CSO
t
CL
t
DH
t
DOE
t
DS
t
STE
CS
Figure 6. Detailed Serial-Interface Timing
MAX1082/MAX1083
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 10-Bit ADCs with Internal Reference
17
Maxim Integrated
SCLK
11 15885812 12 1216 16 1 516
B4B9S0B4B9S0
DIN
SSTRB
DOUT
CS
CONTROL BYTE 0SSSCONTROL BYTE 1
CONVERSION RESULT 1CONVERSION RESULT 0
CONTROL BYTE 2 S ETC
B4B9
Figure 7. Continuous 16-Clock/Conversion Timing
0
0.50
0.25
1.00
0.75
1.25
1.50
0.0001 0.010.001 0.1 1 10
TIME IN SHUTDOWN (s)
REFERENCE POWER-UP DELAY (ms)
MAX1083, V
DD1
=
V
DD2
=
3.0V
C
LOAD
= 20pF
CODE = 1010100000
1000
100
10
1
0.1 101 100 1k 10k
SAMPLING RATE (sps)
SUPPLY CURRENT (µA)
4 CHANNELS
1 CHANNEL
10,000
1000
10
100
1
1 10010 1k 10k 100k
SAMPLING RATE (sps)
SUPPLY CURRENT (µA)
MAX1083, V
DD1
=
V
DD 2
=
3.0V
C
LOAD
= 20pF
CODE = 1010100000
4 CHANNELS
1 CHANNEL
Figure 8. Reference Power-Up Delay vs. Time in Shutdown
Figure 9a. Average Supply Current vs. Conversion Rate with
Internal Reference in FULLPD
Figure 9b. Average Supply Current vs. Conversion Rate with
External Reference in FULLPD
2.5
2.0
1.0
1.5
0.5
0
150
250
100
50
200
300 350
SAMPLING RATE (sps)
SUPPLY CURRENT (mA)
MAX1083, V
DD1
=
V
DD2
=
3.0V
C
LOAD
= 20pF
CODE = 1010100000
REDP
FASTPD
NORMAL OPERATION
Figure 10. Average Supply Current vs. Sampling Rate (in
FASTPD, REDP, and Normal Operation)
MAX1082/MAX1083
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 10-Bit ADCs with Internal Reference
18
Maxim Integrated
Figure 11a. Full Power-Down Timing
REFADJ
1.22V
1.22V
0V
2.5mA
2.5mA
1.3mA OR 0.9mA
DIN
IV
DD1
+ IV
DD2
REF
FULLPD
REDP
WAIT 1.2ms (7 x RC)
FULLPD
1
0
0
11
γ = RC = 17kx 0.01µF
DUMMY CONVERSION
1
1
0
0
0
2.5V
2.5mA
0mA
0mA
2.5V
0V
Figure 11b. FASTPD and REDP Timing
2.5V (ALWAYS ON)
2.5mA
2.5mA
DIN
IV
DD1
+ IV
DD2
REF
REDP
REDP FASTPD
1
1
0
11
1
0
0
1
2.5mA
0.9mA
0.9mA
1.3mA
unipolar operation, and 1LSB = 2.44mV [(2.500V / 2) /
1024] for bipolar operation.
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards;
wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
Figure 15 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at GND. Connect all other analog
grounds to the star ground. Connect the digital system
ground to this ground only at this point. For lowest-
noise operation, the ground return to the star ground’s
power supply should be low impedance and as short
as possible.
High-frequency noise in the V
DD1
power supply may
affect the high-speed comparator in the ADC. Bypass
the supply to the star ground with 0.1µF and 10µF
capacitors close to V
DD1
of the MAX1082/MAX1083.
Minimize capacitor lead lengths for best supply-noise
rejection. If the power supply is very noisy, a 10 resis-
tor can be connected as a lowpass filter (Figure 15).
High-Speed Digital Interfacing with QSPI
The MAX1082/MAX1083 can interface with QSPI using
the circuit in Figure 16 (CPOL = 0, CPHA = 0). This QSPI
circuit can be programmed to do a conversion on each of
the four channels. The result is stored in memory without
taxing the CPU, since QSPI incorporates its own microse-
quencer.
TMS320LC3x Interface
Figure 17 shows an application circuit to interface the
MAX1082/MAX1083 to the TMS320 in external clock
mode. The timing diagram for this interface circuit is
shown in Figure 18.
Use the following steps to initiate a conversion in the
MAX1082/MAX1083 and to read the results:
1) The TMS320 should be configured with CLKX
(transmit clock) as an active-high output clock and

MAX1082ACUE+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 300/400ksps Sgl-Sply 4Ch Serial 10Bit
Lifecycle:
New from this manufacturer.
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