74ACTQ02MTC

74ACTQ02 Quad 2-Input NOR Gate
©1990 Fairchild Semiconductor Corporation www.fairchildsemi.com
74ACTQ02 Rev. 1.4 4
AC Electrical Characteristics
Notes:
5. Voltage range 5.0 is 5.0V ± 0.5V.
6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
separate outputs of the same device. The specification applies to any outputs switching in the same direction,
either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
Capacitance
Symbol Parameter V
CC
(V)
(5)
T
A
= +25°C,
C
L
= 50pF
T
A
= –40°C to +85°C,
C
L
= 50pF
UnitsMin. Typ. Max. Min. Max.
t
PLH
Propagation Delay,
Data to Output
5.0 2.0 5.0 7.5 2.0 8.0 ns
t
PHL
Propagation Delay,
Data to Output
5.0 2.0 5.0 7.5 2.0 8.0 ns
t
OSHL
, t
OSLH
Output to Output Skew
(6)
5.0 0.5 1.0 1.0 ns
Symbol Parameter Conditions Typ. Units
C
IN
Input Capacitance V
CC
= OPEN 4.5 pF
C
PD
Power Dissipation Capacitance V
CC
= 5.0V 74 pF
74ACTQ02 Quad 2-Input NOR Gate
©1990 Fairchild Semiconductor Corporation www.fairchildsemi.com
74ACTQ02 Rev. 1.4 5
FACT™ Noise Characteristics
The setup of a noise characteristics measurement is
critical to the accuracy and repeatability of the tests. The
following is a brief description of the setup used to
measure the noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50pF,
500.
2. Deskew the HFS generator so that no two channels
have greater than 150ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper
loading of the outputs and that the input levels are at
the correct voltage.
4. Set the HFS generator to toggle all but one output at
a frequency of 1MHz. Greater frequencies will
increase DUT heating and effect the results of the
measurement.
Notes:
7. V
OHV
and V
OLP
are measured with respect to ground
reference.
8. Input pulses have the following characteristics:
f = 1MHz, t
r
= 3ns, t
f
= 3ns, skew < 150ps.
Figure 1. Quiet Output Noise Voltage Waveforms
5. Set the HFS generator input levels at 0V LOW and
3V HIGH for ACT devices and 0V LOW and 5V HIGH
for AC devices. Verify levels with an oscilloscope.
V
OLP
/V
OLV
and V
OHP
/V
OHV
:
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually
be the furthest from the ground pin. Monitor the output
voltages using a 50 coaxial cable plugged into a
standard SMB type connector on the test fixture.
Do not use an active FET probe.
Measure V
OLP
and V
OLV
on the quiet output during
worst case transition for active and enable. Measure
V
OHP
and V
OHV
on the quiet output during the worst
case active and enable transition.
Verify that the GND reference recorded on the
oscilloscope has not drifted to ensure the accuracy
and repeatability of the measurements.
V
ILD
and V
IHD
:
Monitor one of the switching outputs using a 50
coaxial cable plugged into a standard SMB type
connector on the test fixture. Do not use an active
FET probe.
First increase the input LOW voltage level, V
IL
, until
the output begins to oscillator steps out a min of 2ns.
Oscillation is defined as noise on the output LOW
level that exceeds V
IL
limits, or on output HIGH levels
that exceed V
IH
limits. The input LOW voltage level at
which oscillation occurs is defined as V
ILD
.
Next decrease the input HIGH voltage level, V
IH
, until
the output begins to oscillate or steps out a min of 2ns.
Oscillation is defined as noise on the output LOW
level that exceeds V
IL
limits, or on output HIGH levels
that exceed V
IH
limits. The input HIGH voltage level at
which oscillation occurs is defined as V
IHD
.
Verify that the GND reference recorded on the
oscilloscope has not drifted to ensure the accuracy
and repeatability of the measurements.
Figure 2. Simultaneous Switching Test Circuit
74ACTQ02 Quad 2-Input NOR Gate
©1990 Fairchild Semiconductor Corporation www.fairchildsemi.com
74ACTQ02 Rev. 1.4 6
Physical Dimensions
Dimensions are in inches (millimeters) unless otherwise noted.
Figure 3. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A

74ACTQ02MTC

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Logic Gates Qd 2-Input NOR Gate
Lifecycle:
New from this manufacturer.
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