MAX1117/MAX1118/MAX1119
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
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nected to an autozero supply. Since the device
requires only a single supply, the negative input of the
comparator is set to equal V
DD
/2. The capacitive DAC
restores the positive input to V
DD
/2 within the limits of 8-
bit resolution. This action is equivalent to transferring a
charge Q
IN
= 16pF x V
IN
from C
HOLD
to the binary-
weighted capacitive DAC, which in turn forms a digital
representation of the analog-input signal.
Input Voltage Range
Internal protection diodes that clamp the analog input
to V
DD
and GND allow the input pins (CH0, CH1) to
swing from (GND - 0.3V) to (V
DD
+ 0.3V) without dam-
age. However, for accurate conversions, the inputs
must not exceed (V
DD
+ 50mV) or be less than (GND -
50mV).
Input Bandwidth
The ADC’s input tracking circuitry has a 4MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Serial Interface
The MAX1117/MAX1118/MAX1119 have a 3-wire serial
interface. The CNVST and SCLK inputs are used to
control the device, while the three-state DOUT pin is
used to access the conversion results.
The serial interface provides connection to microcon-
trollers (µCs) with SPI, QSPI, and MICROWIRE serial
interfaces at clock rates up to 5MHz. The interface sup-
ports either an idle high or low SCLK format. For SPI
and QSPI, set CPOL = CPHA = 0 or CPOL = CPHA = 1
in the SPI control registers of the µC. Figure 5 shows
the MAX1117/MAX1118/MAX1119 common serial-inter-
face connections. See Figures 6a–6d for details on the
serial interface timing and protocol.
Digital Inputs and Outputs
The MAX1117/MAX1118/MAX1119 perform conver-
sions using an internal clock. This frees the µP from the
burden of running the SAR conversion clock and allows
the conversion results to be read back at the µP’s con-
venience at any clock rate up to 5MHz.
The acquisition interval begins with the falling edge of
CNVST. CNVST can idle between conversions in either
a high or low state. If idled in a low state, CNVST must
be brought high for at least 50ns, then brought low to
initiate a conversion. To select CH1 for conversion, the
CNVST pin must be brought high and low for a second
time (Figures 6c and 6d).
After CNVST is brought low, allow 7.5μs for the conver-
sion to be completed. While the internal conversion is in
progress, DOUT is low. The MSB is present at the
DOUT pin immediately after conversion is completed.
The conversion result is clocked out at the DOUT pin
and is coded in straight binary (Figure 7). Data is
clocked out at SCLK’s falling edge in MSB-first format
at rates up to 5MHz. Once all data bits are clocked
out, DOUT goes high impedance (100ns to 500ns after
the rising edge) of the eighth SCLK pulse.
