6A595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
www.allegromicro.com
5
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are V
DD
and Ground)
CLOCK
SERIAL
DATA IN
STROBE
OUTPUT
ENABLE
OUT
N
Dwg. WP-029-2
50%
SERIAL
DATA OUT
DATA
DATA
50%
50%
50%
C
A B
D E
LOW = ALL OUTPUTS ENABLED
p
t
DATA
50%
p
t
LOW = OUTPUT ON
HIGH = OUTPUT OFF
OUTPUT
ENABLE
OUT
N
Dwg. WP-030-2
DATA
10%
50%
PHL
t
PLH
t
HIGH = ALL OUTPUTS DISABLED
90%
f
t
r
t
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), t
su(D)
.......................................... 20 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), t
h(D)
.............................................. 20 ns
C. Clock Pulse Width, t
w(CLK)
............................................. 40 ns
D. Time Between Clock Activation
and Strobe, t
su(ST)
....................................................... 50 ns
E. Strobe Pulse Width, t
w(ST)
.............................................. 50 ns
F. Output Enable Pulse Width, t
w(OE)
................................ 4.5 µs
NOTE – Timing is representative of a 12.5 MHz clock.
Higher speeds are attainable.
Serial data present at the input is transferred to the shift
register on the rising edge of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information
towards the SERIAL DATA OUTPUT.
Information present at any register is transferred to the
respective latch on the rising edge of the STROBE input pulse
(serial-to-parallel conversion).
When the OUTPUT ENABLE input is high, the output
source drivers are disabled (OFF). The information stored in the
latches is not affected by the OUTPUT ENABLE input. With
the OUTPUT ENABLE input low, the outputs are controlled by
the state of their respective latches.
LOGIC SYMBOL
2
G3
C2
SRG8
C1
R
1D
2
OUT
0
OUT
1
OUT
2
OUT
3
OUT
4
OUT
5
OUT
6
OUT
7
SERIAL
DATA OUT
OUTPUT
ENABLE
STROBE
REGISTER
CLEAR
SERIAL
DATA IN
CLOCK
Dw
. FP-043-2
