MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
16 ______________________________________________________________________________________
filter. The MAX4250 provides a low offset voltage (for
high-gain accuracy) and a low noise level. The passive
10Hz filter following the buffer attenuates noise pro-
duced in the voltage reference and buffer stages. This
filtered noise density, which decreases for higher fre-
quencies, meets the noise levels specified for precision
ADC operation.
Unbuffered External Reference Drives
Multiple ADCs
Connecting each REFIN to analog ground disables the
internal reference of each device, allowing the internal
reference ladders to be driven directly by a set of exter-
nal reference sources. Followed by a 10Hz lowpass fil-
ter and precision voltage-divider (Figure 11), the
MAX6066 generates a DC level of 2.500V. The buffered
outputs of this divider are set to 2.0V, 1.5V, and 1.0V,
with an accuracy that depends on the tolerance of the
divider resistors. The three voltages are buffered by the
MAX4252, which provides low noise and low DC offset.
The individual voltage followers are connected to 10Hz
lowpass filters, which filter both the reference voltage
and amplifier noise to a level of 3nHz. The 2.0V and
1.0V reference voltages set the differential full-scale
range of the associated ADCs at 2V
P-P
. The 2.0V and
1.0V buffers drive the ADC’s internal ladder resistances
between them. Note that the common power supply for
all active components removes any concern regarding
power-supply sequencing when powering up or down.
With the outputs of the MAX4252 matching better than
0.1%, the buffers and subsequent lowpass filters can
be replicated to support as many as 32 ADCs. For
applications that require more than 32 matched ADCs,
a voltage reference and divider string common to all
converters is highly recommended.
REFOUT
29
N.C.
REFIN
31
REFP
32
REFN
1
COM
2
0.1μF
0.1μF
0.1μF
0.1μF
2.048V
100μF2
5
3
2
3
1
4
1
MAX1446
N = 1
MAX4250
REFOUT
29
N.C.
REFIN
31
REFP
32
REFN
1
COM
2
0.1μF
0.1μF
0.1μF
0.1μF
MAX1446
N = 1000
0.1μF
162Ω
16.2kΩ
3.3V
1μF
10Hz LOWPASS
FILTER 10Hz LOWPASS
FILTER
NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 1000 ADCs.
2.2μF
10V
0.1μF
0.1μF
3.3V
MAX6062
Figure 10. Buffered External Reference Drives Up to 1000 ADCs
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
______________________________________________________________________________________ 17
Grounding, Bypassing,
__________________and Board Layout
The MAX1446 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side as
the ADC, using surface-mount devices for minimum
inductance. Bypass V
DD
, REFP, REFN, and COM with
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OV
DD
) to OGND. Multilayer
boards with separated ground and power planes pro-
duce the highest level of signal integrity. Consider
using a split ground plane arranged to match the physi-
cal location of the analog ground (GND) and the digital
output driver ground (OGND) on the ADC's package.
The two ground planes should be joined at a single
point so that the noisy digital ground currents do not
interfere with the analog ground plane. The ideal loca-
tion of this connection can be determined experimen-
tally at a point along the gap between the two ground
planes that produces optimum results. Make this con-
nection with a low-value, surface-mount resistor (1Ω to
5Ω), a ferrite bead, or a direct short. Alternatively, all
REFOUT
29
N.C.
REFIN
31
REFP
32
REFN
1
COM
2
0.1μF
0.1μF
0.1μF
330μF
6V
330μF
6V
330μF
6V
10μF
6V
11
4
3
2
3
1
2
1
MAX1446
N = 1
MAX6066
1/4 MAX4252
REFOUT
29
N.C.
REFIN
31
REFP
32
REFN
1
COM
2
0.1μF
0.1μF
0.1μF
MAX1446
N = 32
47Ω
2.0V AT 8mA
1.47kΩ
21.5kΩ
3.3V
1μF
21.5kΩ
21.5kΩ
21.5kΩ
21.5kΩ
NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 32 ADCs.
2.2μF
10V
0.1μF
0.1μF
3.3V
2.0V
10μF
6V
11
4
5
6
7
1/4 MAX4252
47Ω
1.5V AT 0mA
1.47kΩ
3.3V
10μF
6V
11
4
10
9
8
1/4 MAX4252
47Ω
1.0V AT -8mA
1.47kΩ
3.3V
3.3V
MAX4254 POWER-SUPPLY BYPASSING.
PLACE CAPACITOR AS CLOSE AS
POSSIBLE TO THE OP AMP.
0.1μF
1.5V
1.0V
Figure 11. Unbuffered External Reference Drives Up to 32 ADCs
HOLD
ANALOG
INPUT
SAMPLED
DATA (T/H)
T/H
t
AD
t
AJ
TRACK TRACK
CLK
Figure 12. T/H Aperture Timing
MAX1446
ground pins could share the same ground plane if the
ground plane is sufficiently isolated from any noisy, dig-
ital systems ground plane (e.g., downstream output
buffer or DSP ground plane). Route high-speed digital
signal traces away from sensitive analog traces. Keep
all signal lines short and free of 90° turns.
Static Parameter Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function
once offset and gain errors have been nullified. The
MAX1446’s static linearity parameters are measured
using the best-straight-line fit method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
Dynamic Parameter Definitions
Aperture Jitter
Figure 12 depicts the aperture jitter (t
AJ
), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (t
AD
) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 12).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (rms value) to the rms quanti-
zation error (residual error). The ideal, theoretical mini-
mum A/D noise is caused by quantization error only
and results directly from the ADC’s resolution (N bits):
SNR
(MAX)
= 6.02 x N + 1.76
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the rms sig-
nal to the rms noise, which includes all spectral compo-
nents minus the fundamental, the first five harmonics,
and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the rms signal
to all spectral components minus the fundamental and
the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB
is computed from:
Total Harmonic Distortion (THD)
THD is typically the ratio of the rms sum of the input
signal’s first four harmonics to the fundamental itself.
This is expressed as:
where V
1
is the fundamental amplitude, and V
2
through
V
5
are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the rms
amplitude of the fundamental (maximum signal compo-
nent) to the rms value of the next largest spurious com-
ponent, excluding DC offset.
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) inter-
modulation products. The individual input tone levels
are at -6.5dB full scale.
THD
VVVV
V
+++
20
1
2345
2222
log
ENOB
SINAD
=
(.)
.
176
602
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
18 ______________________________________________________________________________________

MAX1446GHJ+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 10-Bit 60Msps 3V High Speed ADC
Lifecycle:
New from this manufacturer.
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