Fremont Micro Devices Preliminary FT25L04/02
© 2014 Fremont Micro Devices Inc. Confidential Rev1.0 DS25L04/02-page10
6. STATUS REGISTER
S7 S6 S5 S4 S3 S2 S1 S0
SRWD Reserved Reserved BP2 BP1 BP0 WEL WIP
The status and control bits of the Status Register are as follows:
WIP bit.
The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status
register progress. When WIP bit sets to 1, the device is busy in program/erase/write status register progress.
When WIP bit sets 0, the device is not in program, erase or write status register .
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1,
the internal Write Enable Latch is set. When set to 0, the internal Write Enable Latch is reset and no Write
Status Register, Program or Erase command is accepted.
BP2, BP1, BP0 bits.
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase commands. These bits are written with the Write Status Register
(WRSR) command. When the Block Protect (BP2, BP1, BP0) bits are set to 1, the relevant memory area (as
defined in Table1.1 or 1.2).becomes protected against Page Program (PP), Sector Erase (SE) and Block
Erase (BE) commands. Chip Erase command will be ignored if one or more of the Block Protect (BP2, BP1,
BP0) bits are 1.
SRWD bit.
The Status Register Write Disable (SRWD) bit is a non-volatile One Time Program(OTP) bit in the status
register that provide another software protection. Once it is set to 1, the Write Status Register (WRSR)
instruction is no longer accepted and the SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only.
SRWD Status register Memory
0
Status register can be written in (WEL
bit is set to "1") and the SRWD,
BP2-BP0 bits can be changed
The protected area cannot be program
or erase
1
The SRWD, BP2-BP0 of status register
bits cannot be changed
The protected area cannot be program
or erase
Fremont Micro Devices Preliminary FT25L04/02
© 2014 Fremont Micro Devices Inc. Confidential Rev1.0 DS25L04/02-page11
7. COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device, beginning with the most
significant bit on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must
be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the
command, this might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven
high after the last bit of the command sequence has been shifted in. For the command of Read, Fast Read,
Read Status Register, and Read Device ID, the shifted-in command sequence is followed by a data-out
sequence. CS# can be driven high after any bit of the data-out sequence is being shifted out.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write
Enable, Write Disable, CS# must be driven high exactly at a byte boundary, otherwise the command is
rejected. That is CS# must driven high when the number of clock pulses after CS# being driven low is an
exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen
and WEL will not be reset.
Table2. Commands
Command Name
Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 n-Bytes
Write Enable 06H
Write Disable 04H
Read Status Register 05H (S7-S0) (continuous)
Write Status Register 01H (S7-S0) (continuous)
Read Data 03H A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte) (continuous)
Fast Read 0BH A23-A16 A15-A8 A7-A0 dummy (D7-D0) (continuous)
Page Program 02H A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte)
Sector Erase 20H A23-A16 A15-A8 A7-A0
Block Erase D8H A23-A16 A15-A8 A7-A0
Chip Erase C7/60H
Manufacturer/Device ID 90H dummy dummy 00H
(MID7-MID0) (DID7-DID0)
(continuous)
Read Identification 9FH
(MID7-MID0)
(JDID15-JDI
D8)
(JDID7-JDID
0)
(continuous)
Fremont Micro Devices Preliminary FT25L04/02
© 2014 Fremont Micro Devices Inc. Confidential Rev1.0 DS25L04/02-page12
Table of ID Definitions:
FT25L04
Operation Code M7-M0 ID15-ID8 ID7-ID0
9FH 0E 60 13
90H 0E 12
FT25L02
Operation Code M7-M0 ID15-ID8 ID7-ID0
9FH 0E 60 12
90H 0E 11

FT25L04T-RB

Mfr. #:
Manufacturer:
Description:
IC FLASH 4M SPI 40MHZ 8TSSOP
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New from this manufacturer.
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