ISL83384ECA-T

7
FN6017.3
March 15, 2005
Interconnection with 3V and 5V Logic
The ISL83384E directly interfaces with 5V CMOS and TTL
logic families. Nevertheless, with the device at 3.3V, and the
logic supply at 5V, AC, HC, and CD4000 outputs can drive
ISL83384E inputs, but ISL83384E outputs do not reach the
minimum V
IH
for these logic families. See Table 3 for more
information.
15kV ESD Protection
All pins on ISL83XXX devices include ESD protection
structures, but the ISL83384E incorporates advanced
structures which allow the RS-232 pins (transmitter outputs
and receiver inputs) to survive ESD events up to 15kV. The
RS-232 pins are particularly vulnerable to ESD damage
because they typically connect to an exposed port on the
exterior of the finished product. Simply touching the port
pins, or connecting a cable, can cause an ESD event that
might destroy unprotected ICs. These new ESD structures
protect the device whether or not it is powered up, protect
without allowing any latchup mechanism to activate, and
don’t interfere with RS-232 signals as large as 25V.
Human Body Model (HBM) Testing
As the name implies, this test method emulates the ESD
event delivered to an IC during human handling. The tester
delivers the charge through a 1.5k current limiting resistor,
making the test less severe than the IEC61000 test which
utilizes a 330 limiting resistor. The HBM method
determines an IC’s ability to withstand the ESD transients
typically present during handling and manufacturing. Due to
the random nature of these events, each pin is tested with
respect to all other pins. The RS-232 pins on “E” family
devices can withstand HBM ESD events to 15kV.
IEC16000-4-2 Testing
The IEC61000 test method applies to finished equipment,
rather than to an individual IC. Therefore, the pins most likely
to suffer an ESD event are those that are exposed to the
outside world (the RS-232 pins in this case), and the IC is
tested in its typical application configuration (power applied)
rather than testing each pin-to-pin combination. The lower
current limiting resistor coupled with the larger charge
storage capacitor yields a test that is much more severe than
the HBM test. The extra ESD protection built into this
device’s RS-232 pins allows the design of equipment
meeting level 4 criteria without the need for additional board
level protection on the RS-232 port.
AIR-GAP DISCHARGE TEST METHOD
For this test method, a charged probe tip moves toward the
IC pin until the voltage arcs to it. The current waveform
delivered to the IC pin depends on approach speed,
humidity, temperature, etc., so it is difficult to obtain
repeatable results. The “E” device RS-232 pins withstand
15kV air-gap discharges.
CONTACT DISCHARGE TEST METHOD
During the contact discharge test, the probe contacts the
tested pin before the probe tip is energized, thereby
eliminating the variables associated with the air-gap
discharge. The result is a more repeatable and predictable
test, but equipment limits prevent testing devices at voltages
higher than 8kV. All “E” family devices survive 8kV contact
discharges on the RS-232 pins.
FIGURE 8. LOOPBACK TEST AT 250Kbps
TABLE 3. LOGIC FAMILY COMPATIBILITY WITH VARIOUS
SUPPLY VOLTAGES
SYSTEM
POWER-SUPPLY
VOLTAGE
(V)
V
CC
SUPPLY
VOLTAGE
(V) COMPATIBILITY
3.3 3.3 Compatible with all CMOS
families.
5 5 Compatible with all TTL and
CMOS logic families.
5 3.3 Compatible with ACT and HCT
CMOS, and with TTL.
ISL83384E outputs are
incompatible with AC, HC, and
CD4000 CMOS inputs.
T1
IN
T1
OUT
R1
OUT
2s/DIV
5V/DIV
V
CC
= +3.3V
C1 - C4 = 0.1F
ISL83384E
8
FN6017.3
March 15, 2005
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP)
GND
TRANSISTOR COUNT
338
PROCESS
Si Gate CMOS
Typical Performance Curves V
CC
= 3.3V, T
A
= 25°C
FIGURE 9. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CAPACITANCE
FIGURE 10. SLEW RATE vs LOAD CAPACITANCE
FIGURE 11. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
FIGURE 12. SUPPLY CURRENT vs SUPPLY VOLTAGE
-6.0
-4.0
-2.0
0
2.0
4.0
6.0
1000 2000 3000 4000 50000
LOAD CAPACITANCE (pF)
TRANSMITTER OUTPUT VOLTAGE (V)
1 TRANSMITTER AT 250Kbps
V
OUT
+
V
OUT
-
1 TRANSMITTER AT 30Kbps
LOAD CAPACITANCE (pF)
SLEW RATE (V/s)
0 1000 2000 3000 4000 5000
5
10
15
20
25
+SLEW
-SLEW
0
5
10
15
20
25
30
45
35
40
0 1000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
SUPPLY CURRENT (mA)
20Kbps
250Kbps
120Kbps
SUPPLY CURRENT (mA)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0
0.5
1.0
1.5
2.0
SUPPLY VOLTAGE (V)
2.5
3.0
3.5
NO LOAD
ALL OUTPUTS STATIC
ISL83384E
9
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6017.3
March 15, 2005
ISL83384E
Shrink Small Outline Plastic Packages (SSOP)
NOTES:
1. Symbols are defined in the MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C A
M
B
S
e
-A-
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
C
H
0.25(0.010) B
M
M
L
0.25
0.010
GAUGE
PLANE
A2
M20.209 (JEDEC MO-150-AE ISSUE B)
20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.068 0.078 1.73 1.99
A1 0.002 0.008’ 0.05 0.21
A2 0.066 0.070’ 1.68 1.78
B 0.010’ 0.015 0.25 0.38 9
C 0.004 0.008 0.09 0.20’
D 0.278 0.289 7.07 7.33 3
E 0.205 0.212 5.20’ 5.38 4
e 0.026 BSC 0.65 BSC
H 0.301 0.311 7.65 7.90’
L 0.025 0.037 0.63 0.95 6
N20 207
0 deg. 8 deg. 0 deg. 8 deg.
Rev. 3 11/02

ISL83384ECA-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC TXRX 2/2 FULL RS232 20SSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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