MP18021HN-LF-Z

MP18021
100V High Frequency
Half-Bridge Gate Driver
MP18021 Rev. 1.11 www.MonolithicPower.com 1
10/20/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
The Future of Analog IC Technology
DESCRIPTION
The MP18021 is a high frequency, 100V half
bridge N-channel power MOSFET driver. Its low
side and high side driver channels are
independently controlled and matched with less
than 5ns in time delay. Under voltage lock-out on
both high side and low side supplies force their
outputs low in case of insufficient supply. The
integrated bootstrap diode reduces external
component count.
FEATURES
Drives N-channel MOSFET half bridge
100V V
BST
voltage range
On-chip bootstrap diode
Typical 16ns propagation delay time
Less than 5ns gate drive matching
Drive 1nF load with 12ns/9ns rise/fall times
with 12V VDD
TTL compatible input
Less than 150A quiescent current
UVLO for both high side and low side
In SOIC8 EPAD and 3×3mm QFN8
Packages
APPLICATIONS
Telecom half bridge power supplies
Avionics DC-DC converters
Two-switch forward converters
Active clamp forward converters
All MPS parts are lead-free, halogen free, and adhere to the RoHS
directive. For MPS green status, please visit MPS website under Quality
Assurance.
“MPS” and “The Future of Analog IC Technology” are Registered
Trademarks of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
MP18021
PWM
CONTROLLER
INH
VSS
INL
DRVL
SW
DRVH
VDD
BST
+12V
48V
CONTROL
DRIVE
LO
DRIVE
HI
ISOLATION
AND
FEEDBACK
SECONDARY
SIDE
CIRCUIT
MP18021100V HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
MP18021 Rev. 1.11 www.MonolithicPower.com 2
10/20/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
ORDERING INFORMATION
Part Number* Package Top Marking Free Air Temperature (T
A
)
MP18021HN
SOIC8EP
MP18021HN
-40C to + 125C
MP18021HQ
QFN8 (3x 3mm)
ABN
-40C to + 125C
* For Tape & Reel, add suffix –Z (e.g. MP18021HN–Z);
For RoHS compliant packaging, add suffix –LF; (e.g. MP18021HN–LF–Z)
For Tape & Reel, add suffix –Z (e.g. MP18021HQ–Z);
For RoHS compliant packaging, add suffix –LF; (e.g. MP18021HQ–LF–Z)
PACKAGE REFERENCE
VDD
BST
DRVH
SW
DRVL
VSS
INL
INH
1
2
3
4
8
7
6
5
TOP VIEW
TOP VIEW
VDD
BST
DRVH
SW
1
2
3
4
DRVL
VSS
INL
INH
8
7
6
5
EXPOSED PAD
ON BACKSIDE
SOIC8EP QFN8
ABSOLUTE MAXIMUM RATINGS
(1)
Supply Voltage (V
DD
).....................-0.3V to +18V
SW Voltage (V
SW
) .........................-5.0V to 100V
BST Voltage (V
BST
) .......................-0.3V to 100V
BST to SW ....................................-0.3V to +18V
DRVH to SW.................................-0.3V to +18V
All Other Pins...................... -0.3V to (V
DD
+0.3V)
Continuous Power Dissipation (T
A
=+25°C)
(2)
SOIC8 (Exposed Pad) ............................... 2.6W
QFN8 (3x3) ................................................ 2.5W
Junction Temperature...............................150C
Lead Temperature ....................................260C
Storage Temperature............... -65°C to +150C
Recommended Operating Conditions
(3)
Supply Voltage V
DD
.....................+9.0V to 16.0V
SW Voltage (V
SW
) ..................-1.0V to 100V-V
DD
SW slew rate......................................<50V/nsec
Operating Junct. Temp (T
J
)...... -40C to +140C
Thermal Resistance
(4)
θ
JA
θ
JC
SOIC8 (Exposed Pad) ............ 48 ...... 10... C/W
QFN8 (3x3)............................. 50 ...... 12... C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature T
J
(MAX), the junction-to-
ambient thermal resistance θ
JA
, and the ambient temperature
T
A
. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by P
D
(MAX)=(T
J
(MAX)-
T
A
)/ θ
JA
. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
MP18021100V HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
MP18021 Rev. 1.11 www.MonolithicPower.com 3
10/20/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
ELECTRICAL CHARACTERISTICS
V
DD
= V
BST
-V
SW
=12V, V
SS
=V
SW
= 0V, No load at DRVH and DRVL, T
A
= +25C, unless otherwise
noted.
Parameter Symbol Condition Min Typ Max Units
Supply Currents
VDD quiescent current I
DDQ
INL=INH=0 100 150 µA
VDD operating current I
DDO
fsw=500kHz 2.8 3.5 mA
Floating driver quiescent current I
BSTQ
INL=INH=0 60 90 µA
Floating driver operating current I
BSTO
fsw=500kHz 2.1 3 mA
Leakage Current I
LK
BST=SW=100V 0.05 1
A
Inputs
INL/INH High 2 2.4 V
INL/INH Low 1 1.4 V
INL/INH internal pull-down
resistance
R
IN
185
k
Under Voltage Protection
VDD rising threshold V
DDR
7.7 8.1 8.5 V
VDD hysteresis V
DDH
0.5 V
(BST-SW) rising threshold V
BSTR
6.7 7.1 7.5 V
(BST-SW) hysteresis V
BSTH
0.55 V
Bootstrap Diode
Bootstrap diode VF @ 100uA V
F1
0.5 V
Bootstrap diode VF @ 100mA V
F2
0.9 V
Bootstrap diode dynamic R R
D
@ 100mA 2.5
Low Side Gate Driver
Low level output voltage V
OLL
I
O
=100mA 0.15 0.22 V
High level output voltage to rail V
OHL
I
O
=-100mA 0.45 0.6 V
V
DRVL
=0V, V
DD
=12V 1.5 A
Peak pull-up current I
OHL
V
DRVL
=0V, V
DD
=16V 2.5 A
V
DRVL
=V
DD
=12V 2.5 A
Peak pull-down current I
OLL
V
DRVL
=V
DD
=16V 3.5 A
Floating Gate Driver
Low level output voltage V
OLH
I
O
=100mA 0.15 0.22 V
High level output voltage to rail V
OHH
I
O
=-100mA 0.45 0.6 V
V
DRVH
=0V, V
DD
=12V 1.5 A
Peak pull-up current I
OHH
V
DRVH
=0V, V
DD
=16V 2.5 A
V
DRVH
=V
DD
=12V 2.5 A
Peak pull-down current I
OLH
V
DRVH
=V
DD
=16V 3.5 A

MP18021HN-LF-Z

Mfr. #:
Manufacturer:
Monolithic Power Systems (MPS)
Description:
Gate Drivers 100V High Frequency Half-Brdge Gate Drvr
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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