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NLSF1174MNR2G

P1-P3P4-P6
© Semiconductor Components Industries, LLC, 2006
May, 2006 − Rev. 5
1 Publication Order Number:
NLSF1174/D
NLSF1174
Hex D Flip−Flop with
Common Clock and Reset
This device consists of six D flip−flops with common Clock and
Reset inputs. Each flip−flop is loaded with a low−to−high transition of
the Clock input. Reset is asynchronous and active low. All
inputs/outputs are standard CMOS compatible.
Features
• Output Drive Compatibility: 10 LSTTL Loads
• Outputs Directly Interface to CMOS
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• MSL Level 1
• Chip Complexity: 162 FET
• Pb−Free Package is Available*
1
2
3
4
Q5V
CC
16 15 14 13
56 78
9
10
11
12
D3
D5
D4
Q2
Q0
D0
Reset
Q3
ClockGND
Q4
D2
Q1
D1
Figure 1. PIN ASSIGNMENT (Top View)
Center pad on bottom may be connected to V
CC
of device.
This pad must be isolated or connected to V
CC
.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
Inputs Output
Reset Clock D Q
FUNCTION TABLE
L
H
H
H
H
LXX
No Change
No Change
H
L
X
X
L
H
L
Device Package Shipping
†
ORDERING INFORMATION
NLSF1174MNR2 QFN−16 3000 / Tape & Ree
l
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
s
Brochure, BRD8011/D.
NLSF1174MNR2G QFN−16
(Pb−Free)
3000 / Tape & Ree
l
NLSF1174 = Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
MARKING DIAGRAM
QFN−16
MN SUFFIX
CASE 485G
16
NLSF
1174
ALYW G
G
1
1
NLSF1174
http://onsemi.com
2
Figure 2. LOGIC DIAGRAM
D0
D1
D2
D3
D4
D5
Q0
Q1
Q2
Q3
Q4
Q5
CLOCK
RESET
DATA
INPUTS
NONINVERTING
OUTPUTS
DESIGN/VALUE TABLE
Design Criteria Value Unit
Internal Gate Count* 40.5 ea
Internal Gate Propagation Delay 1.5 ns
Internal Gate Power Dissipation 5.0
mW
Speed Power Product .0075 pJ
*Equivalent to a two−input NAND gate.
MAXIMUM RATINGS
Parameter Symbol Value Unit
DC Supply Voltage (Referenced to GND) V
CC
*0.5 to )7.0 V
DC Input Voltage (Referenced to GND) V
IN
*1.5 to V
CC
)1.5 V
DC Output Voltage (Referenced to GND) (Note 1) V
OUT
*0.5 to V
CC
)0.5 V
DC Input Current, per Pin I
IN
$20 mA
DC Output Current, per Pin I
OUT
$25 mA
DC Supply Current, V
CC
and GND Pins I
CC
$50 mA
Storage Temperature Range T
STG
*65 to )150 °C
Lead Temperature, 1 mm from Case for 10 Seconds PDIP, SOIC, TSSOP T
L
260 °C
Junction Temperature Under Bias T
J
)150 °C
Thermal Resistance QFN
q
JA
80 °C/W
Power Dissipation in Still Air at 85°C QFN P
D
800 mW
Moisture Sensitivity MSL Level 1
Flammability Rating Oxygen Index: 30 to 35 F
R
UL 94 V−0 @ 0.125 in
ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
V
ESD
u2000
u100
u500
V
Latchup Performance Above V
CC
and Below GND at 85°C (Note 5) I
LATCHUP
$300 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. I
O
absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
6. For high frequency or heavy load considerations, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
NLSF1174
http://onsemi.com
3
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Max Unit
DC Supply Voltage (Referenced to GND) V
CC
2.0 6.0 V
DC Input Voltage, Output Voltage (Referenced to GND) (Note 7) V
IN
, V
OUT
0 V
CC
V
Operating Temperature, All Package Types T
A
*55 )125 °C
Input Rise and Fall Time (Figure 4) V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
t
r
, t
f
0
0
0
1000
500
400
ns
7. Unused inputs may not be left open. All inputs must be tied to a high− or low−logic input voltage level.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Parameter
Test Conditions
V
CC
V
Guaranteed Limit
Uni
t
Symbol
*555C to 255C v855C v1255C
Minimum High−Level Input Voltage V
OUT
= 0.1 V or V
CC
– 0.1 V
|I
OUT
| v 20 mA
V
IH
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
Maximum Low−Level Input Voltage V
OUT
= 0.1 V or V
CC
– 0.1 V
|I
OUT
| v 20 mA
V
IL
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
Minimum High−Level Output Voltage
V
IN
= V
IH
or V
IL
|I
OUT
| v 20 mA
V
OH
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
IN
= V
IH
or V
IL
|I
OUT
| v 4.0 mA
|I
OUT
| v 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
Maximum Low−Level Output Voltage
V
IN
= V
IH
or V
IL
|I
OUT
| v 20 mA
V
OL
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
= V
IH
or V
IL
|I
OUT
| v 4.0 mA
|I
OUT
| v 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
Maximum Input Leakage Current V
IN
= V
CC
or GND I
IN
6.0 $0.1 $1.0 $1.0
mA
Maximum Quiescent Supply Current
(per Package)
V
IN
= V
CC
or GND
I
OUT
= 0 mA
I
CC
6.0 4.0 40 160
mA
8. Information on typical parametric values, along with high frequency or heavy load considerations, can be found in the ON Semiconductor
High−Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Parameter
V
CC
V
Guaranteed Limit
Uni
t
Symbol *555C to 255C v855C v1255C
Maximum Clock Frequency (50% Duty Cycle)
(Figures 4 and 7)
f
max
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
Maximum Propagation Delay, Clock to Q
(Figures 5 and 7)
t
PLH
t
PHL
2.0
4.5
6.0
110
22
19
140
28
24
165
33
28
ns
Maximum Propagation Delay, Reset to Q
(Figures 2 and 7)
t
PLH
t
PHL
2.0
4.5
6.0
110
21
19
140
28
24
160
32
27
ns
Maximum Output Transition Time, Any Output
(Figures 4 and 7)
t
TLH
t
THL
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Maximum Input Capacitance C
in
10 10 10 pF
Power Dissipation Capacitance, per Enabled Output (Note 10) C
PD
Typical @ 255C, V
CC
= 5.0 V
pF
62
9. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
CMOS Data Book (DL129/D).
10.Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
. For load considerations, see the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
P1-P3P4-P6

NLSF1174MNR2G

Mfr. #:
Buy NLSF1174MNR2G
Manufacturer:
ON Semiconductor
Description:
Flip Flops 2-6V CMOS Hex D-Type w/Clock
Lifecycle:
New from this manufacturer.
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