I
NTEGRATED
C
IRCUITS
D
IVISION
CPC5710N
4 www.ixysic.com R03
1.5 Electrical Characteristics
Unless otherwise specified, minimum and maximum
values are guaranteed by production testing
requirements. Typical values, the result of engineering
evaluations, are characteristic of the device and are
provided for informational purposes only. They are not
however, a part of the production testing requirements.
Unless otherwise indicated:
V
DD
= 5V, Temperature = 25°C
1.5.1 AC Characteristics
1.5.2 Detector Threshold Characteristics
1.5.3 LIN
/CMP Input Characteristics
1.5.4 Power Characteristics
Parameter Symbol Conditions Minimum Typical Maximum Unit
Input Impedance
Z
IN
10 - - M
Input offset voltage
V
IO
--40mV
Input offset current
I
IO
I
CM
= 0, No common-mode signal applied.
--35nA
I
CM
= 12A (per lead) signal applied.
- - 125 nA
Output DC bias level
V
OUT_DC
At LINOUT+ or LINOUT-, I
O
= 0.5mA
0.9 1.0 1.1 V
Output Low Voltage
V
OUT
I
O
= 0.5mA
--50mV
Gain
A
V
0 to 20kHz 5.88 6 6.12 -
Common-mode
rejection ratio
CMRR
Common-mode current
12A per lead,
0 to 120Hz
40 - - dB
Equivalent input noise
voltage
V
N
--90-dBm/Hz
Parameter Symbol Conditions Minimum Typical Maximum Unit
Detection threshold
V
IN_DET
I
CM
= 0
675 750 850 mV
I
CM
= ±12A
488 750 1012 mV
Detector hysteresis
V
IN_HYST
I
CM
= 0
300 375 450 mV
Parameter Symbol Conditions Minimum Typical Maximum Unit
Input low voltage
V
IL
--0.8V
Input high voltage
V
IH
2.0 - - V
Input low leakage
current
I
IL
V
IL
= 0.4V
- - -120 A
Input high leakage
current
I
IH
V
IH
= 2.4V
- - -120 A
Parameter Symbol Conditions Minimum Typical Maximum Unit
Supply voltage
V
DD
3.0 - 5.5 V
Supply current
I
DD
All inputs and outputs open - - 10 mA
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2. Using CPC5710N
2.1 LIN/CMP Input
The LIN/CMP input selects the active output, either
the detector output CMPOUT
or the linear outputs,
LINOUT- and LINOUT+. Set LIN
/CMP low for linear
output and high for comparator output. Note that both
outputs cannot be used at once.
With LIN
/CMP at logic low (LIN/CMP = 0), the
amplifier outputs are biased at a nominal 1V
DC
and
CMPOUT
is held high. With LIN/CMP at logic high
(LIN
/CMP = 1), LINOUT+ is 0V and LINOUT- is 2V.
Figure 1. LIN
/CMP Timing for Caller-ID Signal
Reception
2.2 Amplifier Design
Considerations
Amplifier inputs are biased at a nominal 1.25V
DC
, the
internal voltage reference. The internal common-mode
circuitry maintains the average of the inputs at
1.25V
DC
. For example, if one input reaches 1.3V, the
common-mode circuit drives the other input to 1.2V.
2.2.1 Linear Amplifier Gain
Display feature information (caller ID) and voice
signals are coupled through the linear amplifier. In
North America, CID data signals are typically sent
between the first and second ringing signal burst.
Referring to Figure 5., signal gain from tip and ring to
LINOUT+ and LINOUT- is determined by:
where
is the frequency of the signal.
Application Note AN-117 Customize Caller ID Gain and
Ringing Detect Voltage Threshold is a spreadsheet for
trying different component values in this type of circuit.
2.3 Detector Considerations
2.3.1 Ringing Signal Detection
The CPC5710N detector is a full-wave configuration.
Ringing signals will assert the output on both positive
and negative parts of the ringing waveform. Hysteresis
is employed by the internal comparator circuit to
provide noise immunity. The set-up of the detector
causes CMPOUT
output pulses to remain low for most
of the ringing signal positive and negative half-cycles.
CMPOUT
returns high when the ringing signal is near
the zero-voltage crossing.
Figure 2. CMPOUT
Relative to Input
2.3.2 Setting Ringing Detection Threshold
The ringing detection threshold depends on the
component values of the input network. The values for
these components shown in the application circuit are
recommended for typical operation. Referring to
Figure 5., the ringing detection threshold can be
changed according to the following formula:
Caller ID data
LIN/CMP
Signal levels not to scale
2s
500 ms 3s 475 ms 2s
GAIN
CID
dB 20
6R
SNPD
4R
SNP
R
SNPD
+
2 1
fC
SNP

2
--------------------------+
-----------------------------------------------------------------------------------------log=
CMPOUT
Ringing Signal
V
RINGPK
750mV
R
RSNPD
-------------------


4R
SNP
R
SNPD
+
2 1
f
RING
C
SNP

2
--------------------------------------+=
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With the application circuit in Figure 5., the series
capacitors serve to reduce the magnitude of the
high-amplitude, low-frequency ringing signals, while
making the ringing detection threshold of the
CPC5710N variable with the frequency of the ringing
signal. With the circuit as given, CMPOUT
will change
states with a 15Hz ringing signal at approximately
48V
PEAK
. For a 68Hz ringing signal, CMPOUT will
change states with a ringing signal amplitude of
approximately 11.5V
PEAK
.
In applications where CPC5710N will be used only as
a ringing level detector, or if significant attenuation of
the amplified signal can be tolerated, the frequency
variability of the ringing detection threshold can be
reduced by increasing the value of the resistors and
capacitors in series with the input.
Application Note AN-117 Customize Caller ID Gain and
Ringing Detect Voltage Threshold is a spreadsheet for
trying different component values in this circuit for
LITELINK snoop circuit applications.
2.4 Power Quality
CPC5710N works best with a clean power supply. To
clean up power supply noise, IXYS Integrated Circuits
Division recommends using a pi network on the V
DD
pin as shown in Figure 3., if needed.
Figure 3. Optional Power Supply pi Network
Note: For lower-frequency noise, use a 220 H
inductor in series with R100.
3.3 or 5 V
R100
10
To V
Pin 1
DD
A
A
C101
10
FB100
600
200 mA
Ω
C100
1

CPC5710N

Mfr. #:
Manufacturer:
IXYS Integrated Circuits
Description:
Communication ICs - Various Phone Line Monitor
Lifecycle:
New from this manufacturer.
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